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smsc com20020i 3.3v rev.e 1 revision 09-11-06 datasheet com20020i 3.3v rev.e 5mbps arcnet (ansi 878.1) controller with 2k x 8 on-chip ram datasheet product features ? new features: - data rates up to 5 mbps - programmable reconfiguration times ? 28 pin plcc and 48 pin tqfp packages; lead-free rohs compliant packages also available ? ideal for industrial/factory/building automation and transportation applications ? deterministic, (ansi 878.1), token passing arcnet protocol ? minimal microcontroller and media interface logic required ? flexible interface for use with all microcontrollers or microprocessors ? automatically detects ty pe of microcontroller interface ? 2kx8 on-chip dual port ram ? command chaining for packet queuing ? sequential access to internal ram ? software programmable node id ? eight, 256 byte pages allow four pages tx and rx plus scratch-pad memory ? next id readable ? internal clock scaler and clock multiplier for adjusting network speed ? operating temperat ure range of -40 o c to +85 o c ? 3.3v power supply with 5v tolerant i/o ? self-reconfiguration protocol ? supports up to 255 nodes ? supports various network topologies (star, tree, bus...) ? cmos, single +3.3v supply ? duplicate node id detection ? powerful diagnostics ? receive all packets mode ? flexible media interface: - traditional hybrid interface for long distances at 2.5mbps - rs485 differential driver interface for low cost, low power, high reliability ordering information order number(s): com20020i 3vljp for 28 pin plcc * package com20020i 3v-dzd for 28 pin plcc * lead-free rohs compliant package com20020i 3v-hd for 48 pin tqfp package com20020i 3v-ht for 48 pin tqfp lead-free rohs compliant package * tqfp package is recommended for new design downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 2 revision 09-11-06 datasheet 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? 2006 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc products are included as a means of illustrating typical applications. consequently, complete information sufficient for cons truction purposes is not necessarily given. al though the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent rights or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "ter ms of sale agreement"). the pr oduct may contain design defects o r errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are available upon r equest. smsc products are not designed, intended, authorized or warranted for us e in any life support or other application where product fai lure could cause or contribute to personal injury or severe property damage. any and al l such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copi es of this document or other sm sc literature, as well as the terms of sale agreement, may be obtained by visiting smscs website at http://www.smsc.co m. smsc is a registered trademark of standard microsystems corp oration (smsc). product names and company names are the tradem arks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, a nd any and all warranties arising from any course of de aling or usage of trade. in no event shall smsc be liab le for any direct, incidental, indi rect, special, punitive, or consequential damages; or for lost data, profit s, savings or revenues of any kind; regardless of the form of action, whether based on contract; to rt; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 3 revision 09-11-06 datasheet table of contents chapter 1 general de script ion................................................................................................................5 chapter 2 pin configu rations ...................................................................................................................6 chapter 3 description of pin funct ions ...............................................................................................8 chapter 4 protocol d escription........................................................................................................... 11 4.1 n etwork p rotocol ............................................................................................................................... ....11 4.2 d ata r ates ............................................................................................................................... .................11 4.2.1 selecting clock frequencie s above 2. 5 mbps .................................................................................... 1 1 4.3 n etwork r econfiguration ........................................................................................................................12 4.4 b roadcast m essages ............................................................................................................................... .12 4.5 e xtended t imeout f unction ......................................................................................................................12 4.6 l ine p rotocol ............................................................................................................................... .............13 chapter 5 system des cription ............................................................................................................. ...15 5.1 m icrocontroller i nterface .....................................................................................................................15 5.2 t ransmission m edia i nterface ..................................................................................................................19 chapter 6 functional d escription........................................................................................................2 4 6.1 m icrosequencer ............................................................................................................................... .........24 6.2 internal registers ...................................................................................................................... ......25 6.3 i nternal r am ............................................................................................................................... ...............35 6.4 c ommand c haining ............................................................................................................................... ......40 6.5 i nitialization s equence ..............................................................................................................................4 2 6.6 i mproved d iagnostics ............................................................................................................................... .42 chapter 7 operational d escriptio n .....................................................................................................45 7.1 m aximum g uaranteed r atings * .................................................................................................................45 7.2 d c e lectrical c haracteristics ................................................................................................................45 chapter 8 timing diagrams ................................................................................................................ .......48 chapter 9 package outlines ............................................................................................................... ....63 chapter 10 appendix a..................................................................................................................... ..............65 chapter 11 appendix b..................................................................................................................... ..............68 chapter 12 appendix c..................................................................................................................... ..............69 12.1 s oftware i dentification of the com20020i 3v r ev d and r ev e ............................................................69 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 4 revision 09-11-06 datasheet list of figures figure 1 - com20020i 3v oper ation .............................................................................................. .............................10 figure 2 - multiplexed, 8051-like bus interface with rs -485 inte rface.......................................................... .............16 figure 3 - non-multiplexed, 6801-like bus interface with rs-485 interf ace ...................................................... .........17 figure 4 - high speed cpu bu s timing - inte l cpu mode .......................................................................... .................18 figure 5 - com20020i 3v network usin g rs-485 differential transceivers......................................................... .........20 figure 6 - dipulse wavefo rm for data of 1-1-0.................................................................................. .........................20 figure 7 - internal block diagram.............................................................................................. ...................................22 figure 8 C sequential access oper ation......................................................................................... .............................35 figure 9 C ram buffer pa cket config uration..................................................................................... ...........................38 figure 10 - command chaining status register queue............................................................................. ...................40 figure 11 - multiplexed bus, 68xx-l ike control signal s; read cycle............................................................. ..............48 figure 12 - multiplexed bus, 80xx-l ike control signal s; read cycle............................................................. ..............49 figure 13 - multiplexed bus, 68xx-l ike control signal s; write cycle............................................................ ...............50 figure 14 - multiplexed bus, 80xx-l ike control signal s; write cycle............................................................ ...............51 figure 15 - non-multiple xed bus, 80xx-like cont rol signals; read cycle......................................................... ..........52 figure 16 - non-multiple xed bus, 80xx-like cont rol signals; read cycle......................................................... ..........53 figure 17 - non-multiple xed bus, 68xx-like cont rol signals; read cycle......................................................... ..........54 figure 18 - non-multiple xed bus, 68xx-like cont rol signals; read cycle......................................................... ..........55 figure 19 - non-multiplex ed bus, 80xx-like contro l signals; wr ite cy cle ........................................................ ...........56 figure 20 - non-multiplex ed bus, 80xx-like contro l signals; wr ite cy cle ........................................................ ...........57 figure 21 - non-multiplex ed bus, 68xx-like contro l signals; wr ite cy cle ........................................................ ...........58 figure 22 - non-multiplex ed bus, 68xx-like contro l signals; wr ite cy cle ........................................................ ...........59 figure 23 C normal mode tran smit or rece ive ti ming ............................................................................. ..................60 figure 24 C backplane mode tr ansmit or rece ive ti ming.......................................................................... .................61 figure 25 C ttl input timing on xt al1 pi n ...................................................................................... .........................62 figure 26 C reset a nd interrupt timing ......................................................................................... ..............................62 figure 27 - 28 pin plcc package di mensio ns..................................................................................... .......................63 figure 28 - 48 pin tq fp package outline........................................................................................ ...........................64 figure 29 - effect of the ef bit on the ta/ri bit.............................................................................. .........................66 figure 30 - example of interface circuit diagram to isa bus .................................................................... ................68 list of tables table 1 - typi cal media ........................................................................................................ ........................................23 table 2 - read r egister su mmary................................................................................................ ...............................24 table 3 - write r egister su mmary ............................................................................................... ................................25 table 4 - stat us register ...................................................................................................... ...............................28 table 5 - diagnostic status register ........................................................................................... ...................29 table 6 - comm and register ..................................................................................................... ...........................30 table 7 - address poin ter high register ........................................................................................ ...............................30 table 8 - address po inter low register......................................................................................... ...............................31 table 9 - sub a ddress register ................................................................................................ .......................31 table 10 - configur ation re gister .............................................................................................. ..................................31 table 11 - setup 1 register .................................................................................................... ..............................33 table 12 - setup 2 register .................................................................................................... ..............................34 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 5 revision 09-11-06 datasheet chapter 1 general description smsc's com20020i 3v is a member of the family of embedded arcnet controllers from standard microsystems corporation. the device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial and embedded control environments using an arcnet protocol engine. the flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the com20020i 3v make it the only true network controller optimized for use in industrial and embedded applications. using a n arcnet protocol engine is the ideal solution for embedded control applications because it provides a dete rministic token-passing protocol, a highly reliable and proven networking scheme, and a data ra te of up to 5 mbps when using the com20020i 3v. a token-passing protocol provides predictable response times because each network eve nt occurs within a predetermined time interval, based upon the number of nodes on the network. the deterministic nature of arcnet is essential in real time applications. the integration of the 2kx8 ram buffer on-chip, the command ch aining feature, the 5 mbps maximum data rate, and the internal diagnostics make the com20020i 3v the highest performance embedded communications device available. with only one com20020 i 3v and one microcontroller, a complete communications node may be implemented. for more details on the arcnet protocol engine and traditional dipulse sig naling schemes, please refer to the arcnet local area network standard , available from standard microsystems corporation or the arcnet designer's handbook , available from datapoint corporation. for more detailed information on cabling options including rs485, transformer-coupled rs-485 and fib er optic interfaces, please refer to the following technical note which is availabl e from standard microsystems corporation: technical note 7-5 - cabling guidelines for the com20020i 3v ulanc. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 6 revision 09-11-06 datasheet chapter 2 pin configurations 2423 22 21 20 19 18 17 16 15 14 13 nrd/nds nwr/dir ncs nintr nreset in ntxen rxin npulse2 npulse1 xtal2 xtal1 vdd 25 24 23 22 21 20 19 n c s n i n tr n r e s e t i n v s s n tx e n r x i n n p u l s e 2 567891011 a d 1 v s s a d 2 d 3 d 4 d 5 d 6 1817 16 15 14 13 12 npulse 1 xtal2 xtal1 vdd vss n/c d7 12 3 4 5 6 7 8 9 10 11 12 a0/nmux a1 a2/ale ad0 ad1 ad2 d3d4 d5 d6 d7 vss 2627 28 1 2 3 4 nwr/dir nrd/nds vdd a2/ale ad0 a1 a0/nmux packages: 24-pin dip or 28-pin plcc ordering information: com20019 package type: p = plastic, ljp = plcc temp range: (blank) = commercial: 0c to +70c i = industrial: -40c to +85c device type: 20019 = universa l local area ne twork controller (with 2k x 8 ram) p i package: 28-pin plcc ordering information: com20020i 3v p package type: p = plastic, ljp = plcc temp range: 1 = industrial: -40 c to 75 c device type: 20020 = universal local area network (with 2k x 8 ram) com20020i 3v 28 pin plcc downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 7 revision 09-11-06 datasheet note: bustmg pin is only tqfp package 4847 46 45 44 43 42 41 40 39 38 37 1314 15 16 17 18 19 20 21 22 23 24 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 n/cn/c a2/ale a1 a0/nmux vdd n/c vss n/c nrd/nds vdd nwr/dir d7 n/c n/c n/c n/c vss n/c vdd xtal1xtal2 vss npulse1 ad0 ad1 n/c ad2 n/c vss d3 vdd d4d5 vss d6 ncs vdd nintr n/c vdd nreset vss ntxen rxin n/c bustmg npulse2 com20020i 48 pin tqfp com20020i 3v 48 pin tqfp downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 8 revision 09-11-06 datasheet chapter 3 description of pin functions pin no name symbol i/o description plcc tqfp microcontroller interface 1, 2, 3 44, 45, 46 address 0-2 a0/nmux a1 a2/ale in in in on a non-multiplexed mode, a0-a2 are address input bits. (a0 is the lsb) on a multiplexed address/data bus, nmux tied low, a1 is left open, and ale is tied to the address latch enable signal. a1 is connected to an internal pull-up resistor. 4, 5, 6, 8, 9, 10, 11, 12 1, 2, 4, 7, 9, 10, 12, 13 data 0-7 ad0-ad2, d3-d7 i/o on a non-multiplexed bus, these signals are used as the lower byte data bus lines. on a multiplexed address/data bus, ad0-ad2 act as the address lines (latched by ale) and as the low data lines. d3-d7 are always used for data only. these signals are connected to internal pull-up resistors. 26 37 nwrite/ direction nwr/dir in nwr is for 80xx cpu, nwr is write signal input. active low. dir is for 68xx cpu, dir is bus direction signal input. (low: write, high: read.) 27 39 nread/ ndata strobe nrd/nds in nrd is for 80xx cpu, nrd is read signal input. active low. nds is for 68xx cpu, nds is data strobe signal input. active low. 23 31 nreset in nreset in hardware reset signal. active low. 24 34 ninterrupt nintr out interrupt signal output. active low. 25 36 nchip select ncs in chip select i nput. active low. - 26 read/write bus timing select bustmg in read and write bus access timing mode selecting signal. status of this signal effects cpu timing. l: high speed timing mode (only for non-multiplexed bus) h: normal timing mode this signal is connected to internal pull-up registers. note: bustmg pin does not exist in plcc package. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 9 revision 09-11-06 datasheet pin no name symbol i/o description plcc tqfp transmission media interface 18 19 24 25 npulse 1 npulse 2 npulse1 npulse2 out i/o in normal mode, these acti ve low signals carry the transmit data information, encoded in pulse format as dipulse waveform. in backplane mode, the npulse1 signal driver is programmable (push/pull or open-drain), while the npulse2 signal provides a clock with frequency of doubled data rate. npulse1 is connected to a weak internal pull-up resistor on the open/drain driver in backplane mode. 20 28 receive in rxin in this signal carries the receive data information from the line transceiver. 21 29 ntransmit enable ntxen out transmission enable signal. active polarity is programmable through the npulse2 pin. npulse2 floating before power-up; ntxen active low npulse2 grounded before power-up; ntxen active high (this option is only available in back plane mode) 16 17 21 22 crystal oscillator xtal1 xtal2 in out an external crystal should be connected to these pins. oscillation frequency range is from 10 mhz to 20 mhz. if an external ttl clock is used instead, it must be connected to xtal1 with a 390ohm pull-up resistor, and xtal2 should be left floating. 15, 28 8, 20, 32, 43 power supply vdd pwr +3.3 volt power supply pins. 7, 14, 22 6, 11, 18, 23, 30, 41 ground vss pwr ground pins. 13 3, 5, 14-17, 19, 27, 33, 35, 38, 40, 42, 47, 48 n/c n/c non-connection downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 10 revision 09-11-06 datasheet figure 1 - com20020i 3v operation invitation to transmit to this id? y n free buffer enquiry to this id? soh? yn yn ri? write sid to buffer did =0? did =id? write buffer with packet crc ok? length ok? did =0? did =id? send ack n y n y n y n broadcast enabled? n y n no activity for 41 us? y n set nid=id start timer: t=(255-id) activity on line? y n t=0? set ri ri? tr a n s mi t nak tr a n s mi t ack set nid=id write id to ram buffer send reconfigure burst power on reconfigure timer has timed out start reconfiguration timer (420 ms)* ta ? broadcast? tr a n s m i t free buffer enquiry no activity pass the tok en set ta y n ack? nak? 1 no activity n y increment nid send packet was packet broadcast? no activity n ack? set tma set ta x 73 us for 37.4 us? for 37.4 us? for 37.4 us? y n n y y n n y n n n n 1 y y y y yy y n y read node id id refers to the identification number of the id assigned to this no de. nid refers to the next identification number that receives the token after this id passes it. -- - - sid refers to the source identification. did refers to the destination identification. soh refers to the start of header character; preceeds all data packets. - yn * reconfig timer is programmable via setup2 register bits 1, 0. note - all time values are valid for 5 mbps. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 11 revision 09-11-06 datasheet chapter 4 protocol description 4.1 network protocol communication on the network is based on a token passing protocol. establishment of the network configuration and management of the network protocol are handled entirely by the com20020i 3v's internal microcoded sequencer. a processor or intelligent peripheral transmits data by simply loading a data packet and its destination id into the com20020i 3v's internal ram buffer, and issuing a command to enable the transmitter. when the com20020i 3v next receives the token, it verifies that the receiving node is ready by first transmitting a free buffer enquiry message. if the receiving node transmits an acknowledge message, the data packet is transmitted followed b y a 16-bit crc. if the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a negative acknowledge message and the transmitter passes the token. once it has been established that the receiving node can accept the packet and transmission is complete, the receiving node verifies the packet. if the packet is received successfully, the receiving node transmits an acknowledge message (or nothing if it is not received successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of t he packet. an interrupt mask permits the com20020i 3v to generate an interrupt to the processor when selected status bits become true . figure 1 is a flow chart illustrating the internal operation of the com20020i 3v connected to a 20 mhz crystal oscillator. 4.2 data rates the com20020i 3v is capable of supporting data rates from 156.25 kbps to 5 mbps. the following protocol description assumes a 5 mbps data rate. to attain the faster data rates, the clock frequency may be doubled by the internal clock multiplier (see next section). for slower data rates, an internal clock divider scales down the clock frequency. thus all timeout values are scaled as shown in the following table: example: idle line timeout @ 5 mbps = 41 s. idle line timeout for 156.2 kbps is 41 s * 32 = 1.3 ms internal clock frequency clock prescaler data rate timeout scaling factor (multiply by) 40 mhz div. by 8 5 mbps 1 20 mhz div. by 8 div. by 16 div. by 32 div. by 64 div. by 128 2.5 mbps 1.25 mbps 625 kbps 312.5 kbps 156.25 kbps 2 4 8 16 32 4.2.1 selecting clock fre quencies above 2.5 mbps to realize a 5 mbps network, an external 40 mhz clock must be input. however, since 40 mhz is near the frequency of fm radio band, it is not practical for use for noise emission reasons. therefore, higher frequency clocks are generated from the 20 mhz crystal as selected through two bits in the setup2 register, ckup as shown below. the selected clock is supplied to the arcnet controller. ckup clock frequency (data rate) 0 20 mhz (up to 2.5mbps) default (bypass) 1 40 mhz (up to 5mbps) this clock multiplier is powered-down (bypassed) on defau lt. after changing the ckup bit, the arcnet core operation is stopped and the internal pll in the clock generator is awakened and it starts to gener ate the 40 mhz. the lock out time of the internal pll is 8usec typically. after more than 8 sec (this wait time is defined as 1 msec in this data sheet), it is necessary to write command data '18h' to the command register to re-start the arcnet core operation. this clock generator is called clock multiplier. changing the ckup bit must be one time or less after releasing hardware reset. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 12 revision 09-11-06 datasheet the ef bit in the setup2 register must be set when the data rate is over 5 mbps. 4.3 network reconfiguration a significant advantage of t he com20020i 3v is its ability to adapt to ch anges on the network. whenever a new node is activated or deactivated, a network reconfiguration is performed. when a new com20020i 3v is turned on (creating a new active node on the network), or if the com20020i 3v has not received an invitation to transmit for 420ms, or if a software reset occurs, the com20020i 3v causes a network reconfiguration by sending a reconfigure burst consisting of eight marks and one space repeated 765 times. the purpose of this burst is to terminate all activity on the network. since this burst is longer than any other type of transmission, the burst will interfere with the next invitation to tr ansmit, destroy the token and keep any other node from assuming control of the line. when any com20020i 3v senses an idle line for greater than 41 s, which occurs only when the token is lost, each com20020i 3v starts an internal timeout equal to 73 s times the quantity 255 minus its own id. the com20020i 3v starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing the destination node id. if the timeout expire s with no line activity, the com20020i 3v starts sending invitation to transmit with the destination id (did) equal to the currently stored ni d. within a given network, only one com20020i 3v will timeout (t he one with the highest id number). after sending the invitation to transmit, the com20020i 3v waits for activity on the line. if there is no activity for 37.4 s, the com20020i 3v increments the nid value and transmits another invitation to transmit using the nid equal to the did. if activity appears before the 37.4 s timeout expires, the com20020i 3v re leases control of the line. during network reconfiguration, invitations to transmit are sent to all nids (1-255). each com20020i 3v on the network will finally have saved a nid value equal to the id of the com20020i 3v that it released control to. at this point, control is passed directly from one node to the next with no wasted invitations to transmit being sent to id's not on the network, until the next networ k reconfiguration occurs. when a node is powered off, the previous node attempts to pass t he token to it by issuing an invitation to transmit. since this node does not respond, the previous node ti mes out and transmits another invitation to transmit to an incremented id and eventually a response will be received. the network reconfiguration time depends on the number of nodes in the network, the propagation delay between nodes, and the highest id number on the network, but is typically within the range of 12 to 30.5 ms. 4.4 broadcast messages broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously. id zero is reserved for this feature and no node on the net work can be assigned id zero. to broadcast a message, the transmitting node's processor simply loads the ram buffer with the data packet and sets the did equal to zero. figure 4 illustrates the position of each byte in the packet with the did residing at address 0x01 or hex of the current page selected in the "enable transmit from page fnn" command. each individual node has the ability to ignore broadcast messages by setting the most signi ficant bit of the "enable receive to page fnn" command to a logic "0". 4.5 extended timeout function there are three timeouts associated with the com20020i 3v operation. the v alues of these timeouts are controlled by bits 3 and 4 of the configuration register and bit 5 of the setup 1 register. response time the response time determines the maximum propagation delay allowed between any two nodes, and should be chosen to be larger than the round trip propagation delay between the two furthest nodes on the network plus the maximum turn around time (the time it takes a particular com20020i 3v to start sending a message in response to a received messa ge) which is approximately 6.4 s. the round trip propagation delay is a fu nction of the transmission media and network topology. for a typical system using rg62 coax in a baseband system, a one way cable propagation delay of 15.5 s translates to a distance of about 2 miles. the flow chart in figure 1 uses a value of 37.4us (15.5 + 15.5 + 6.4) to determine if any node will respond. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 13 revision 09-11-06 datasheet idle time the idle time is associated with a network reconfiguration. figure 1 illustrates that during a network reconfiguration one node will continually transmit invitations to transmit until it encounters an active node. all other nodes on the network must distinguish between this operation and an entirely idle line. duri ng network reconfiguration, activity will appear on the line every 41 s. this 41 s is equal to the response time of 37.4 s plus the time it takes the com20020i 3v to start retransmitting another message (usually another invitation to transmit). reconfiguration time if any node does not receive the token within the reconfiguration time, the node will initiate a network reconfiguration. the et2 and et1 bits of the configuration register allow the network to operate over longer distances than the 2 miles stated earlier. the logic levels on these bits control the maximu m distances over which the com20020i 3v can operate by controlling the three timeout values described above. for proper network operation, all com20020i 3v's connected to the same network must have the same response time, idle time, and reconfiguration time. 4.6 line protocol the arcnet line protocol is considered isochronous because each byte is preceded by a sta rt interval and ended with a stop interval. unlike asynchronous protocols, there is a constant amount of time separating each data byte. on a 5 mbps network, each byte takes exactly 11 clock intervals of 200ns each. as a result, one byte is transmitted ev ery 2.2us and the time to transmit a message can be precisely determined. the line idles in a spac ing (logic "0") condition. a logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 100ns duration. a transmi ssion starts with an alert burst consisting of 6 unit intervals of mark (logic "1"). eight bit data characters are then sent, with each character preceded by 2 unit intervals of mark and one unit interval of space. five types of transmission can be performed as described below: invitations to transmit an invitation to transmit is used to pass the token from one node to another and is sent by the following sequen ce: ? an alert burst ? an eot (end of transmis sion: ascii code 04h) ? two (repeated) did (destination id) characters alert burst eot did did free buffer enquiries a free buffer enquiry is used to ask another node if it is ab le to accept a packet of data. it is sent by the following sequence: ? an alert burst ? an enq (enquiry: ascii code 85h) ? two (repeated) did (destination id) characters alert burst enq did did data packets a data packet consists of the actual data being sent to another node. it is sent by the follo wing sequence: ? an alert burst ? an soh (start of header--ascii code 01h) ? an sid (source id) character ? two (repeated) did (destination id) characters ? a single count character which is the 2's complement of the number of data byt es to follow if a short packet is sent, or 00h followed by a count character if a long packet is sent. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 14 revision 09-11-06 datasheet ? n data bytes where count = 256-n (or 512-n for a long packet) ? two crc (cyclic redundancy check) characters. the crc polynomial used is: x 16 + x 15 + x 2 + 1. a lert burst soh sid did did count data data crc crc acknowledgements an acknowledgement is used to acknowledge reception of a packet or as an affirmative response to free bu ffer enquiries and is sent by the following sequence: ? an alert burst ? an ack (acknowledgement--ascii code 86h) character alert burst ack negative acknowledgements a negative acknowledgement is used as a negative respon se to free buffer enquiries and is sent by the following sequence: ? an alert burst ? a nak (negative acknowledgement--ascii code 15h) character alert burst nak downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 15 revision 09-11-06 datasheet chapter 5 system description 5.1 microcontroller interface the top halves of figure 2 and figure 3 illustrate typical com20020i 3v interfaces to the microcontrollers. the interfaces consist of a 8-bit data bus, an address bus and a control bus. in order to support a wide range of microcontrollers without requiring glue logic and without in creasing the number of pins, the com20020i 3v automatically detects and adapts to the type of microcontroller being used. upon hardware reset, the com20020i 3v first determin es whether the read and write control signals are separate read and write signals (like the 80xx) or direction and data strobe (like the 68xx). to determine the type of control signals, the device requires the software to execute at least one write access to external memory before attempting to access the com20020i 3v . the device defaults to 80xx-like signals. once the type of control signals are de termined, the com20020i 3v remains in this interface mode until the next hardware reset occurs. the second determination the com20020i 3v makes is whether the bus is multiplexed or non-multiplexed. to determine the type of bus, the device requires the software to write to an odd memory location followed by a read from an odd location before attempting to access the com20020i 3v. the signal on the a0 pin during the odd location access tells the com20020i 3v the type of bus. since multiplexed operation requires a0 to be active low , activity on the a0 line tells the com20020i 3v that the bus is non-multiplexed. the device def aults to multiplexed operation. both determinations may be made simultaneously by performing a write followed by a read operation to an odd location within the com20020i 3v address space 20020 registers. once the type of bus is determined, the com20020i 3v remains in this interface mode until hardware reset occurs. whenever ncs and nrd are activated, the preset determinations are assumed as final and will no t be changed until hardware reset. refer to chapter 3 description of pin functions for details on the related signals. all accesses to the internal ram and the internal registers are controlled by the com20020i 3v. the inter nal ram is accessed via a pointer-based scheme (refer to the sequential access memory section), and the internal registers are accessed via direct addressing. many peripherals are not fast enough to take advantage of high-speed microcontrollers. since microcontrollers do not typically have ready inputs, standa rd peripherals cannot extend cycles to extend the access time. the access time of the com20020i 3v, on the other hand, is so fast that it does not need to limit the speed of the microcontroller. the com20020i 3v is designed to be flexible so that it is independent of the microcon troller speed. the com20020i 3v provides for no wait state arbitration via direct addressing to its internal regi sters and a pointer based addressing scheme to access its internal ram. the pointer may be used in auto -increment mode for typical sequential buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the r am. the data within the ram is accessed through the data register. data being read is prefetche d from memory and placed into the data register for the microcontroller to read. it is important to notice that only by writing a new address pointer (writing to an address pointer low), one obtains the contents of com20020i 3v internal ram. performing only read from the data register does not load new data from the internal ram . during a write operation, the data is stored in the data register and then written into memory. whenever the pointer is loaded for reads with a new va lue, data is immediately prefetched to prepare for the first read operation. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 16 revision 09-11-06 datasheet figure 2 - multiplexed, 8051-like bus interface with rs-485 interface ad0-ad7 nint1 reset nrd nwr a15 ad0-ad2, d3-d7 ncs nreset nrd/nds nwr/dir nintr a2/bale ale xtal1 xtal2 gnd rxin npulse1 npulse2 ntxen 8051 com20022 differential driver configuration media interface may be replaced with figure a, b or c. * rxin npulse1 npulse2 txen gnd +5v 100 ohm backplane configuration figure a rxin npulse1 figure b receiver hfd3212-002 2 +5v 7 6 tra ns mi t t e r hfe4211-014 +5v 3 2 fiber interface (st connectors) 26 7 note: com20022 must be in backplane mode 75176b or equiv. a0/nmux 27 pf 27 pf xtal2 xtal1 20 mhz xtal downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 17 revision 09-11-06 datasheet figure 3 - non-multiplexed, 6801-like bus interface with rs-485 interface d0-d7 nirq1 nres nios r/nw a7 d0-d7 a0/nmux a0 xtal1 xtal2 a1 a1 ncs nreset nrd/nds nwr/ndir nintr a2/bale a2 rxin npulse1 npulse2 txen gnd differential driver configuration 6801 com20022 media interface may be replaced with figure a, b or c. * 75176b or equiv. x t a l1 x t a l2 27 pf 27 pf 20m h z x t a l rxin npulse1 npulse2 ntxen gnd traditional hybrid configuration rxin npulse1 npulse2 17, 19, 4, 13, 14 5.6k 1/2w 5.6k 1/2w 0.01 uf 1kv 12 11 -5v 0.47 uf 10 uf + 3 0.47 uf + +5v uf 10 6 figure c hyc9088 hyc9068 or n/c *valid for 2.5 mbps only. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 18 revision 09-11-06 datasheet high speed cpu bus timing support high speed cpu bus support was added to the com20020i 3v. the reasoning behind this is as follows: with the host interface in non-mult iplexed bus mode, i/o address and chip select signals must be st able before the read signal is active and remain after the read signal is inactive. but the high speed cpu bus timing doesn't adhere to these timings. for example, a risc type single chip microcont roller (like the hitachi superh series) changes i/o address at the same time as the read signal . therefore, several external logic ics would be required to connect to this microcontroller. in addition, the diagnostic status (diag) register is cleared automatically by reading itself. the internal diag register read signal is generated by decoding the address (a2-a0), chip select (ncs) and read (nrd) signals. the decoder will generate a noise spike at the above ti ght timing. the diag register is clear ed by the spike signal without reading itself. this is unexpected operation. reading the intern al ram and next id register have the same mechanism as reading the diag register. therefore, the address decode and host in terface mode blocks were modified to fit the above cpu interface to support high speed cpu bus timing. in intel cpu mode (nrd, nw r mode), 3 bit i/o address (a2-a0) and chip select (ncs) are sampled internally by flip-flops on the falling edge of the internal delayed nrd signal. the internal real read signal is the more delayed nrd signal. but the rising edge of n rd doesn't delay. by this modification, the internal real address and chip select are stable while the internal real read signal is active. refer to figure 4 below. figure 4 - high speed cpu bu s timing - intel cpu mode the i/o address and chip select signals, which are supplied to the data output logic, ar e not sampled. also, the nrd signal is not delayed, because the above sampling and del aying paths decrease the data access time of the read cycle. the above sampling and delaying signals are supplied to the read pulse generation logic which generates the clearing pulse for the diagnostic register and generates the starting pulse of the ram arbitration. typical delay time between nrd and nrd1 is around 15ns and between nrd1 and nrd2 is around 10ns. longer pulse widths are needed due to these delays on nrd si gnal. however, the cpu can insert some wait cycles to extend the width without any impact on performance. the rbustmg bit was added to disable/enable the high speed cpu read function. it is defined as: rbustmg=0, disabled (default); rbustmg=1, enabled. the bustmg pin (tqfp package only) is used to support this function. it is used to enable/disable the high speed cpu read and write function. it is defined as: bustmg = 0, the high spee d cpu read and write operations are enabled; bustmg = 1, the high speed cpu read and write oper ations are disabled if the rbustmg bit is 0. if bustmg = 1 and rbustmg = 1, high speed cpu read operations are enabled (see def inition of rbustmg bit below). a2-a0, ncs nrd delayed nrd (nrd1) sampled a2-a0, ncs more delayed nrd (nrd2) valid valid downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 19 revision 09-11-06 datasheet in the motorola cpu mode (dir, nds mode), the same modifications apply. z for 28-pin plcc package (bustmg is tied to 1 internally) rbustmg bit bus timing mode 0 normal speed cpu read and write 1 high speed cpu read and normal speed cpu write z for 48-pin tqfp package bustmg pin rbustmg bit bus timing mode 0 x high speed cpu read and write 1 0 normal speed cpu read and write 1 1 high speed cpu read and normal speed cpu write 5.2 transmission media interface the bottom halves of figure 2 and figure 3 illustrate the co m20020i 3v interface to the transmission media used to connect the node to the network. table 1 - typical media lists different types of cable which are suitable for arcnet applications. the user may interface to the cabl e of choice in one of three ways: traditional hybrid interface the traditional hybrid interface is that which is used with previous arcnet devices. t he hybrid interface is recommended if the node is to be placed in a network with other hybrid-interfaced nodes. th e traditional hybrid interface is for use with nodes operating at 2.5 mbps only. th e transformer coupling of the hybrid offers isolation for the safety of the system and offers high common mode rejection. the traditional hybrid interface uses circuits li ke smsc's hyc9068 or hyc9088 to transfer the pulse-enco ded data between the cable and the com20020i 3v. the com20020i 3v transmits a logic "1" by generating two 100ns non-overlapping negative pulses, npulse1 and npulse2. lack of pulses indicates a logic "0". the npulse1 and npulse2 signals are sent to the hybri d, which creates a 200ns dipulse signal on the media. a logic "0" is transmitted by the absence of the dipulse. during reception, the 200ns dipulse appearing on the media is coupled through the rf transformer of the lan driver, wh ich produces a positive pulse at the rxin pin of the com20020i 3v. the pulse on the rxin pin represents a logic "1". lack of p ulse represents a logic "0". typically, rxin pulses occur at multiples of 400ns. the com20020i 3v can tolerate distortion of plus or minus 100ns and still correctly capture and convert the rxin pulses to nrz format. figure 5 illustrates the events which occur in transmission or reception of data consisting of 1, 1, 0. please refer to tn7-5 C cabling guidelines for the com20020i 3v ulanc , available from smsc, for recommended cabling distance, termination, and node count for arcnet nodes. backplane configuration the backplane open drain configuration is recommended for cost-sensitive, short-distance applic ations like backplanes and instrumentation. this mode is advantageous because it saves components, cost, and power. since the backplane configuration encodes data differently than the traditional hybrid configuratio n, nodes utilizing the backplane configuration cannot communicate directly with nodes utilizing the traditional hy brid configuration. the backplane configuration does not isolate the node from the media nor protects it from co mmon mode noise, but common mode noise is less of a problem in short distances. the com20020i 3v supplies a programmable output driver for backplane mode operation. a push /pull or open drain driver can be selected by programming the p1mode bit of th e setup 1 register (see regist er descriptions for details). the com20020i 3v defaults to an open drain output. the backplane configuration provides for direct connection between the com20020i 3v and the media. o nly one pull-up resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual node). the npulse1 signal, in this mode, is an ope n drain or push/pull driver and is used to directly drive the media. it issues a 200ns negative pulse to transmit a logic "1". note that when used in the open-drain mode, the com20020i 3v does not have a fail/safe input on the rxin pin. the npulse1 signal actu ally contains a weak pull-up resistor. this pull-up should not take the place of the resistor required on the media for open drain mode. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 20 revision 09-11-06 datasheet figure 5 - com20020i 3v network using rs-485 differential transceivers figure 6 - dipulse waveform for data of 1-1-0 20mhz clock (for ref. only) npulse1 npulse2 dipulse rxin 10 100ns 100ns 200ns 400ns 1 com20022i 3v com20022i 3v com20022i 3v +vcc rbias +vcc +vcc rbias rbias rt rt 75176b or equiv. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 21 revision 09-11-06 datasheet in typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. the rxin signal is directly connected to the cable via an internal schmitt trigger. a negative pulse on this input indicates a logic "1". lack of pulse indicates a logic "0". for typical single-ended backplane applications, rxin is connected to npulse1 to make the serial backplane data line. a ground line (from the coax or twisted pair) should run in para llel with the signal. for applications requiring different treatment of the receive signal (like fil tering or squelching), npulse1 and rxin remain as independent pins. external differential drivers/receivers for increased range and common mode noise rejection, for example, would require the signals to be independent of one another. when the device is in backplane mode, the clock provided by the npulse2 signal may be used for encoding the data into a different encoding scheme or other synchronous operations needed on the serial data stream. differential driver configuration the differential driver configuration is a special case of the backplane mode. it is a dc coup led configuration recommended for applications like car-area networks or other cost-sensitive applications which do not require di rect compatibility with existing arcnet nodes and do not require isolation. the differential driver configuration cannot communicate directly with nodes utilizing the tradition al hybrid configuration. like the backplane configuration, the differential driver configuration does not isolat e the node from the media. the differential driver interface includes a rs485 driver/receiver to transfer the data between the cable and the com20020i 3v. the npulse1 signal transmits the data, provided the transmit enable signal is active. the npulse1 signal issues a 200ns (at 2.5mbps) negative pulse to transmit a logic "1". lack of pulse indicates a logic "0" . the rxin signal receives the data, the transmitter portion of the com20020i 3v is disabled during r eset and the npulse1, npulse2 and ntxen pins are inactive. programmable txen polarity to accommodate transceivers with active high enable pins, the com20020i 3v contains a programmable txen output. to program the txen pin for an active high pulse, the npulse2 pin should be connected to ground. t o retain the normal active low polarity, npulse2 should be left open. the polarity determination is made at pow er on reset and is valid only for backplane mode operation. the npulse2 pin should remain grounded at all times if an active high p olarity is desired. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 22 revision 09-11-06 datasheet figure 7 - internal block diagram micro- sequencer and working registers status/ command register reset logic reconfiguration timer node id logic oscillator tx/rx logic additional registers address decoding circuitry 2k x 8 ad0-ad2, bus arbitration circuitry npulse1 npulse2 ntxen nintr nreset ram a 0 / n m u x a 1 a 2 / b a l e nrd/nds nwr/dir ncs d3-d7 rxin xtal1 xtal2 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 23 revision 09-11-06 datasheet table 1 - typical media cable type nominal impedance attenuation per 1000 ft. at 5 mhz rg-62 belden #86262 93 5.5db rg-59/u belden #89108 75 7.0db rg-11/u belden #89108 75 5.5db ibm type 1* belden #89688 150 7.0db ibm type 3* telephone twisted pair belden #1155a 100 17.9db comcode 26 awg twisted pair part #105-064-703 105 16.0db *non-plenum-rated cables of th is type are also available. note: for more detailed information on cabling options including rs-485, transforme r-coupled rs-485 and fiber optic interfaces, please refer to tn7-5 C cablin g guidelines for the com20020i 3v ulanc, available from standard microsystems corporation. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 24 revision 09-11-06 datasheet chapter 6 functional description 6.1 microsequencer the com20020i 3v contains an internal microsequencer whic h performs all of the contro l operations necessary to carry out the arcnet protocol. it consists of a clock gen erator, a 544 x 8 rom, a progr am counter, two instruction registers, an instruction decoder, a no-op genera tor, jump logic, and reconfiguration logic. the com20020i 3v derives a 10 mhz and a 5 mhz clock from t he output clock of the clock multiplier. these clocks provide the rate at which the instructio ns are executed within the com20020i 3v. the 10 mhz clock is the rate at which the program counter operates, whil e the 5 mhz clock is the rate at which the instructions are executed. the microprogram is stored in the rom and the instructions are fetched and then placed into the instruction registers. one register holds the opcode, while the other holds the i mmediate data. once the instruction is fetched, it is decoded by the internal instruction decoder, at which poin t the com20020i 3v proceeds to execute the instruction. when a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is complete. when a jump in struction is encountered, the program counter is loaded with the jump address from the rom. the com20020i 3v c ontains an internal reconfiguration timer which interrupts the microsequencer if it has timed ou t. at this point the program counter is cleared and the myrecon bit of the diagnostic status register is set. table 2 - read register summary register msb read lsb addr status ri/tri x/ri x/ta po r test recon tma ta/ tta 00 diag. status my-recon dupid rcv- act token exc-n ak tentid new next id x 01 address ptr high rd-data auto- inc x x x a10 a9 a8 02 address ptr low a7 a6 a5 a4 a3 a2 a1 a0 03 data d7 d6 d5 d4 d3 d2 d1 d0 04 sub adr (r/w)* (r/w)* x x x sub-ad 2 sub- ad1 sub-a d0 05 config- uration reset cche n txen et1 et2 back-p lane sub- ad1 sub-a d0 06 tentid tid7 tid6 tid5 tid4 tid3 tid2 tid1 tid0 07-0 node id nid7 nid6 nid5 nid4 nid3 nid2 nid1 nid0 07-1 setup1 p1 mode four naks x rcv- all ckp3 ckp2 ckp1 slow- arb 07-2 next id nxt id7 nxt id6 nxt id5 nxt id4 nxt id3 nxt id2 nxt id1 nxt id0 07-3 setup2 rbus-tmg x x ckup ef no-syn c rcn- tm1 rcm-t m2 07-4 note*: (r/w) these bits can be written or read. for more information see appendix c. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 25 revision 09-11-06 datasheet table 3 - write register summary addr msb write lsb register 00 ri/tr1 0 0 0 excnak reco n new nextid ta/ tta interrupt mask 01 c7 c6 c5 c4 c3 c2 c1 c0 command 02 rd-da ta auto- inc 0 0 0 a10 a9 a8 address ptr high 03 a7 a6 a5 a4 a3 a2 a1 a0 address ptr low 04 d7 d6 d5 d4 d3 d2 d1 d0 data 05 (r/w)* (r/w)* 0 0 0 sub-a d2 sub- ad1 sub- ad0 subadr 06 rese t cchen txen et1 et2 back- plane sub- ad1 sub- ad0 config- uration 07-0 tid7 tid6 tid5 tid4 tid3 tid2 tid1 tid0 tentid 07-1 nid7 nid6 nid5 nid4 nid3 nid2 nid1 nid0 nodeid 07-2 p1-mo de four naks 0 rcv- all ckp3 ckp2 ckp1 slow- arb setup1 07-3 0 0 0 0 0 0 0 0 test 07-4 rbus- tmg 0 0 ckup ef no- sync rcn- tm1 rcn- tm0 setup2 note*: (r/w) these bits can be written or read. for more information see appendix c. 6.2 internal registers the com20020i 3v contains 14 internal registers. table 2 and table 3 illustrate the com20020i 3v register map. all undefined bits are read as undefined and must be written as logic "0". interrupt mask register (imr) the com20020i 3v is capable of generating an interrupt signal when certain status bits become true. a write to the imr specifies which status bits will be enabled to generate an interrupt. the bit positions in the imr are in the same p osition as their corresponding status bits in the status register and diagnostic status register. a logic "1" in a particular position enables the corresponding interrupt. the status bits capable of generating an interrupt include the receiver inhibited bit, new next id bit, excessive nak bit, reconfiguration timer bit, and transmitter available bi t. no other status or diagnostic status bits can generate an interrupt. the six maskable status bits are anded with their respective mask bits, and the results are ored to p roduce the interrupt signal. an ri or ta interrupt is mask ed when the corresponding mask bit is reset to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. a recon interrupt is cleared when the "clear flags" command is issued. an excnak interru pt is cleared when the "por clear flags" command is issued. a new next id interrupt is cleared by reading the next id regist er. the interrupt mask register defaults to the value 0000 0000 upon hardware reset. data register this read/write 8-bit register is used as the channel through which the data to and from the ram passes. the data is placed in or retrieved from the address location presently sp ecified by the address pointer. the contents of the data register are undefined upon hardware reset. in case of read operation, the data register is loaded with the contents of com20020i 3v internal memory upon writing address pointer low only once. tentative id register the tentative id register is a read/write 8-bit register accessed when the sub address bits are set up accordingly (please refer to the configuration register and sub adr register). the tentative id register can be used while the node is on-line to build a network map of those nodes existing on the network. it minimizes the need fo r operator downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 26 revision 09-11-06 datasheet interaction with the network. the node determines the ex istence of other nodes by placing a node id value in the tentative id register and waiting to see if the tentative id bit of the diagnostic status registe r gets set. the network map developed by this method is only valid for a short period of time, since nodes may join or depart from the network a t any time. when using the tentative id feature, a node cannot detect the existence of the next logical n ode to which it passes the token. the next id register will hold the id value of that node. the tentative id register defaults to the value 0000 0000 upon hardware reset only. node id register the node id register is a read/write 8-bit register accessed when the sub address bits are set up accordingly (ple ase refer to the configuration register and sub adr register). the node id register contains the uni que value which identifies this particular node. each node on the network must have a unique node id va lue at all times. the duplicate id bit of the diagnostic status register helps the user find a unique node id. refer to the initialization seq uence section for further detail on the use of the dupid bit. the core of the com20020i 3v does not wake up unt il a node id other than zero is written into the n ode id register. during this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node. once a non-zero nodei d is placed into the node id register, the core wakes up but will not join the network until the txen bit of the configuration register is s et. while the transmitter is disabled, the receiver po rtion of the device is still functional and will provide the user with useful information about the network. the node id register defaults to the value 0000 0000 upon hardware rese t only. next id register the next id register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly (please refer to the configuration register and sub adr register). the next id register holds t he value of the node id to which the com20020i 3v will pass the token. when used in conjunction with the tentative id register , the next id register can provide a complete network map. the next id register is updated each time a nod e enters/leaves the network or when a network reconfiguration occurs. each time the microsequencer updates the next id register, a new next id interrupt is generated. this bit is cleared by reading the ne xt id register. default value is 0000 0000 upon hardware or software reset. status register the com20020i 3v status register is an 8-bit read-only register. all of the bits, except f or bits 5 and 6, are software compatible with previous smsc arcnet devices. in previous smsc arcnet devices the extended timeout status was provided in bits 5 and 6 of the status register. in the com20020i 3v, the com20020, the com90c66, and the com90c165, com20020-5, com20051 and com20051+ these bits exist in and are controlled by the config uration register. the status register contents are defined as in table 4, but are defined differently during the command chaining operation. please refer to the command chaining section for the definition of the status register during command chaining operation. the status register defaults to the value 1xx1 0001 upon either hardware or software reset. diagnostic status register the diagnostic status register contains seven read-only bits which help the user troubleshoot the network or node operation. various combinations of these bits and the txen bit of the configuration register represent different situations. all of these bits, except the excessive nack bit and the new next id bit, are reset to logic "0 " upon reading the diagnostic status register or upon software or hardware reset. the excnak bit is reset by the "por cle ar flags" command or upon software or hardware reset. the diagnostic status register defaults to the value 0000 000x upon either hardware or software reset. command register execution of commands are initiated by performing microcontroller writes to th is register. any combinations of written data other than those listed in table 5 are not permitted and may result in incorrect chip and/or network operation. address pointer registers these read/write registers are each 8-bits wide and are used for addressing the internal ram. new pointer addresses should be written by first writing to the high register and then writing to the low regist er because writing to the low register loads the address. the contents of the address pointer high and low registers a re undefined upon hardware reset. writing to address pointer low loads the address. configuration register the configuration register is a read/write register which is used to confi gure the different modes of the com20020i 3v. the configuration register defaults to the value 0001 1000 upon hardware reset only. subad0 and subad1 poin t to the selection in register 7. sub-address register downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 27 revision 09-11-06 datasheet the sub-address register is new to the com20020i 3v, previously a reserved register. bits 2, 1 and 0 are used to select one of the registers assigned to address 7h. subad1 and subad0 already exist in the c onfiguration register on the com20020b. they are exactly same as those in the sub-address register. if the subad1 and subad0 bits in the configuration register are changed, the subad1and subad0 in the sub-address register are also changed. subad2 is a new sub-address bit. it is used to access the 1 new set up register, setup2. this register is selected by setting subad2=1. the subad2 bit is cleared automat ically by writing the configuration register. setup 1 register the setup 1 register is a read/write 8-bit register accessed when the sub address bi ts are set up accordingly (see the bit definitions of the configuration register). the setup 1 register allows the user to change the network speed (data rate) or the arbitration speed independently, invoke the receive all feature and change the npu lse1 driver type. the data rate may be slowed to 156.25kbps and/or the arbitration speed may be slowed by a factor of two . the setup 1 register defaults to the value 0000 0000 upon hardware reset only. setup 2 register the setup 2 register is new to the com2 0020i 3v. it is an 8-bit read/write register accessed when the sub address bits subad[2:0] are set up accordingly (see the bit definitions of the sub address register). t his register contains bits for various functions. the ckup bit select the clock to be generated from the 20 mhz crystal. the rbustmg bit is used to disable/enable fast read function for high speed cpu bus support. the ef bit is used to enable the new timing for certain functions in the com20020i 3v (if ef = 0, the ti ming is the same as in the com20020i 3v rev. b). see appendix a. the nosync bit is used to enable the nosync function during initia lization. if this bit is reset, the line has to be idle for the ram initialization sequence to be written. if set, the line does not have to be idle for the initialization sequence to be wr itten. see appendix a. the rcntm[1,0] bits are used to set the time-out period of the recon timer. pr ogramming this timer for shorter time periods has the benefit of shortened network reconfiguration periods. the ti me periods shown in the table on the following page are limited by a maximum number of nodes in the network. these time-out period values are for 5mbps. for other data rates, scale the time-out period time values accordingly; the maximum node count remains the same. rcntm1 rcntm0 time-out period max node count 0 0 420 ms up to 255 nodes 0 1 105 ms up to 64 nodes 1 0 52.5 ms up to 32 nodes 1 1 26.25 ms* up to 16 nodes* note*: the node id value 255 must exist in the netwo rk for the 26.25 ms time-out to be valid. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 28 revision 09-11-06 datasheet table 4 - status register bit bit name symbol description 7 receiver inhibited ri this bit, if high, indicates that the receiver is not enabled because either an "enable receive to page fnn" command was never issued, or a packet has been deposited into the ram buffer page fnn as specified by the last "enable receive to page fnn" command. no messages will be received until this command is issued, and once the message has been received, the ri bit is set, thereby inhibiting the receiver. the ri bit is cleared by issuing an "enable receive to page fnn" command. this bit, when set, will cause an interrupt if the corresponding bit of the interrupt mask register (imr) is also set. when this bit is set and another station attempts to send a packet to this station, this station will send a nak. 6,5 (reserved) these bits are undefined. 4 power on reset por this bit, if high, indicates that the com20020i 3v has been reset by either a software reset, a hardware reset, or writing 00h to the node id register. the por bit is cleared by the "clear flags" command. 3 test test this bit is intended for test and diagnostic purposes. it is a logic "0" under normal operating conditions. 2 reconfiguration recon this bit, if high, indicates that the line idle timer has timed out because the rxin pin was idle for 41 s. the recon bit is cleared during a "clear flags" command. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. the interrupt service routine should consist of examining the myrecon bit of the diagnostic status register to determine whether there are consecutive reconfigurations caused by this node. 1 transmitter message acknowledged tma this bit, if high, indicates that th e packet transmitted as a result of an "enable transmit from page fnn" command has been acknowledged. this bit should only be considered valid after the ta bit (bit 0) is set. broadcast messages are never acknowledged. the tma bit is cleared by issuing the "enable transmit from page fnn" command. 0 transmitter available ta this bit, if high, indicates that the transmitter is available for transmitting. this bit is set when the last byte of scheduled packet has been transmitted out, or upon execution of a "disable transmitter" command. the ta bit is cleared by issuing the "enable transmit from page fnn" command after the node next receives the token. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 29 revision 09-11-06 datasheet table 5 - diagnostic status register bit bit name symbol description 7 my reconfiguration my- recon this bit, if high, indicates that a past reconfiguration was caused by this node. it is set when the lost token timer times out, and should be typically read following an interrupt caused by recon. refer to the improved diagnostics section for further detail. 6 duplicate id dupid this bit, if high, indicates that the value in the node id register matches both destination id characters of the token and a response to this token has occurred. trailing zero's are also verified. a logic "1" on this bit indicates a duplicate node id, thus the user should write a new value into the node id register. this bit is only useful for duplicate id detection when the device is off line, that is, when the transmitter is disabled. when the device is on line this bit will be set every time the device gets the token. this bit is reset automatically upon reading the diagnostic status register. refer to the improved diagnostics section for further detail. 5 receive activity rcvact this bit, if high, indicates that data activity (logic "1") was detected on the rxin pin of the device. refer to the improved diagnostics section for further detail. 4 token seen token this bit, if high, indicates that a token has been seen on the network, sent by a node other than this one. refer to the improved diagnostic section for further detail. 3 excessive nak excnak this bit, if high, indicates that either 128 or 4 negative acknowledgements have occurred in response to the free buffer enquiry. this bit is cleared upon the "por clear flags" command. reading the diagnostic status register does not clear this bit. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. refer to the improved diagnostics section for further detail. 2 tentative id tentid this bit, if high, indicates that a response to a token whose did matches the value in the tentative id register has occurred. the second did and the trailing zero's are not checked. since each node sees every token passed around the network, this feature can be used with the device on-line in order to build and update a network map. refer to the improved diagnostics section for further detail. 1 new next id new nxtid this bit, if high, indicates that the next id register has been updated and that a node has either joined or left the network. reading the diagnostic status register does not clear this bit. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. the bit is cleared by reading the next id register. 0 (reserved) this bit is undefined. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 30 revision 09-11-06 datasheet table 6 - command register data command description 0000 0000 clear transmit interrupt this command is used only in the command chaining operation. please refer to the command chaining section for definition of this command. 0000 0001 disable transmitter this command will cancel any pending transmit command (transmission that has not yet started) and will set the ta (transmitter available) status bit to logic "1" when the com20020i 3v next receives the token. 0000 0010 disable receiver this command will cancel any pending receive command. if the com20020i 3v is not yet receiving a packet, the ri (receiver inhibited) bit will be set to logic "1" the ne xt time the token is received. if packet reception is already underway, reception will run to its normal conclusion. b0fn n100 enable receive to page fnn this command allows the com20020i 3v to receive data packets into ram buffer page fnn and resets the ri status bit to logic "0". the values placed in the "nn" bits indicate the page that the data will be received into (page 0, 1, 2, or 3). if the value of "f" is a logic "1", an offset of 256 bytes will be added to that page specified in "nn", allowing a finer resolution of the buffer. refer to the selecting ram page size sect ion for further detail. if the value of "b" is logic "1", the device will also receive broadcasts (transmissions to id zero). the ri status bit is set to logic "1" upon successful reception of a message. 00fn n011 enable transmit from page fnn this command prepares the com20020i 3v to begin a transmit sequence from ram buffer page fnn the next time it receives the token. the values of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3). if "f" is logic "1", an offset of 256 bytes is the start of the page specified in "nn", allowing a finer resolution of the buffer. refer to the selecting ram page size section for furthe r detail. when this command is loaded, the ta and tma bits are reset to logic "0". the ta bit is set to logic "1" upon completion of the transmit sequence. the tma bit will have been set by this time if the device has received an ack from the destination node. the ack is strictly hardware level, sent by the receiving node before its microcontroller is even aware of message reception. refer to figure 1 for details of the transmit sequence and its relation to the ta and tma status bits. 0000 c101 define configuration this command defines the maximum length of packets that may be handled by the device. if "c" is a logic "1", the device handles both long and short packets. if "c" is a logic "0", the device handles only short packets. 000r p110 clear flags this command resets certain status bits of the com20020i 3v. a logic "1" on "p" resets the por status bit and the excnak diagnostic status bit. a logic "1" on "r" resets the recon status bit. 0000 1000 clear receive interrupt this command is used only in the command chaining operation. please refer to the command chaining section for definition of this command. 0001 1000 start internal operation this command restarts the stopped internal operation after changing ckup bit. table 7 - address pointer high register downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 31 revision 09-11-06 datasheet bit bit name symbol description 7 read data rddata this bit tells the com20020i 3v whether the following access will be a read or write. a logic "1" prepares the device for a read, a logic "0" prepares it for a write. 6 auto increment autoinc this bit controls whether the address pointer will increment automatically. a logic "1" on this bit allows automatic increment of the pointer after each access, while a logic "0" disables this function. please refer to the sequential access memory section for further detail. 5-3 (reserved) these bits are undefined. they must be 0. 2-0 address 10-8 a10-a8 these bits hold the upper three address bits which provide addresses to ram. table 8 - address pointer low register bit bit name symbol description 7-0 address 7-0 a7-a0 these bits hold the lower 8 address bits which provide the addresses to ram. table 9 - sub address register bit bit name symbol description 7-3 reserved these bits are undefined. they must be 0. 2,1,0 sub address 2,1,0 subad 2,1,0 these bits determine which register at address 07 may be accessed. the combinations are as follows: subad2 subad1 subad0 register 0 0 0 tentative id (same 0 0 1 node id as in 0 1 0 setup 1 config 0 1 1 next id register) 1 0 0 setup 2 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved subad1 and subad0 are exactly the same as exist in the configuration register. subad2 is cleared automatically by writing the configuration register. table 10 - configuration register bit bit name symbol description 7 reset reset a software reset of the com20020i 3v is executed by writing a logic "1" to this bit. a soft ware reset does not reset the microcontroller interface mode, nor does it affect the configuration register. the only registers that the software reset affect are the status register, the next id register, and the diagnostic status register. this bit must be brought back to logic "0" to release the reset. 6 command chaining enable cchen this bit, if high, enables the command chaining operation of the device. please refer to the command chaining section for further details. a low level on this bit ensures software compatibility with previous smsc arcnet devices. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 32 revision 09-11-06 datasheet bit bit name symbol description 5 transmit enable txen when low, this bit disables transmissions by keeping npulse1, npulse2 if in non-backplane mode, and ntxen pin inactive. when high, it enables the above signals to be activated during transmissions. this bit defaults low upon reset. this bit is typically enabled once the node id is determined, and never disabled during normal operation. please refer to the improved diagnostics section for details on evaluating network activity. 4,3 extended timeout 1,2 et1, et2 these bits allow the network to operate over longer distances than the default maximum 2 miles by controlling the response, idle, and reconfiguration times. all nodes should be configured with the same timeout values for proper network operation. for the com20020i 3v with a 20 mhz crystal oscillator, the bit combinations follow: et2 0 0 1 1 et1 0 1 0 1 response time ( s) 596.6 298.4 149.2 37.4 idle time ( s) 656 328 164 41 reconfig time (ms) 840 840 840 420 note: these values are for 5mbps and rcntmr[1,0]=00. reconfiguration time is changed by the rcntmr1 and rcntmr0 bits. 2 backplane back- plane a logic "1" on this bit puts the device into backplane mode signaling which is used for open drain and differential driver interfaces. 1,0 sub address 1,0 subad 1,0 these bits determine which register at address 07 may be accessed. the combinations are as follows: subad1 subad0 register 0 0 tentative id 0 1 node id 1 0 setup 1 1 1 next id see also the sub address register. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 33 revision 09-11-06 datasheet table 11 - setup 1 register bit bit name symbol description 7 pulse1 mode p1mode this bit determines the type of pulse1 output driver used in backplane mode. when high, a push/pull output is used. when low, an open drain output is used. the default is open drain. 6 four nacks four nacks this bit, when set, will cause the exnack bit in the diagnostic status register to set after four nacks to free buffer enquiry are detected by the com20020i 3v. this bit, when reset, will set the exnack bit after 128 nacks to free buffer enquiry. the default is 128. 5 reserved do not set. it must be 0. 4 receive all rcvall this bit, when set, allows the com20020i 3v to receive all valid data packets on the network, regardless of their destination id. this mode can be used to implement a network monitor with the transmitter on- or off-line. note that acks are only sent for packets received with a destination id equal to the com20020i 3v's programmed node id. this feature can be used to put the com20020i 3v in a 'listen-only' mode, where the transmitter is disabled and the com20020i 3v is not passing tokens. defaults low. 3,2,1 clock prescaler bits 3,2,1 ckp 3,2,1 these bits are used to determine the data rate of the com20020i 3v. the following table is for a 20 mhz crystal: (clock multiplier is bypassed) ckp3 0 0 0 0 1 ckp2 0 0 1 1 0 ckp1 0 1 0 1 0 divisor 8 16 32 64 128 speed 2.5mbs 1.25mbs 625kbs 312.5kbs 156.25kbs note: the lowest data rate achievable by the com20020i 3v is 156.25kbs. defaults to 000 or 2.5mbs. for clock multiplier output clock speed greater than 20 mhz, ckp3, ckp2 and ck p1 must all be zero. 0 slow arbitration select slowarb this bit, when set, will divide the arbitration clock by 2. memory cycle times will increase when slow arbitration is selected. note: for clock multiplier output clock speeds greater than 40 mhz, slowarb must be set. de faults to low. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 34 revision 09-11-06 datasheet table 12 - setup 2 register bit bit name symbol description 7 read bus timing select rbustmg this bit is used to disable/enable the high speed cpu read function for high speed cpu bus support. rbustmg=0: disable (defau lt), rbustmg=1: enable. that is, if bustmg (pin 26: only for tqfp package) = 1 and rbustmg = 1, high speed cpu read operations are enabled. it does not influence write operation. high speed cpu read operation is only for non-multiplexed bus. 6,5 reserved these bits are undefined. they must be 0. 4 clock multiplier ckup higher frequency clocks are generated from the 20 mhz crystal through the selection of these two bits as shown. this clock multiplier is powered-down on default. after changing the ckup bit, the arcnet core operation is stopped and the internal pll in the clock multiplier is awakened and it starts to generate the 40 mhz. the lock out time of the internal pll is 8 sec typically. after 1 ms it is necessary to write command data '18h' to command register for re-starting the arcnet core operation. caution: changing the ckup bit must be one time or less after releasing a hardware reset. ckup clock frequency (data rate) 0 20 mhz (up to 2.5mbps) default 1 40 mhz (up to 5mbps) note: after changing the ckup bit, it is necessary to write a command data '18h' to the command register. because after changing the ckup bits, the internal operation is stopped temporarily. the writing of the command is to start the operation. these initializing steps are shown below. 1) hardware reset (power on) 2) change ckup bit 3) wait 1msec (wait until stable oscillation) 4) write command '18h' (start internal operation) 5) start initializing routine (execute existing software) 3 enhanced functions ef this bit is used to enable the new enhanced functions in the com20020i 3v. ef = 0: disable (d efault), ef = 1: enable. if ef = 0, the timing and function is the same as in the com20020i, revision b. see appendix a. ef bit must be 1 if the data rate is over 5mbps. ef bit should be 1 for new design customers. ef bit should be 0 for replacement customers. 2 no synchronous nosync this bit is used to enable the sync command during initialization. nosync= 0, e nable (default) the line must be idle for the ram initialization sequence to be written. nosync= 1, disable:) the line does not have to be idle for the ram initialization sequence to be written. see appendix a. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 35 revision 09-11-06 datasheet bit bit name symbol description 1,0 reconfiguration timer 1, 0 rcntm1,0 these bits are used to program the reconfiguration timer as a function of maximum node count. these bits set the time out period of the reconfiguration timer as shown below. the time out periods shown are for 5 mbps. rcntm1 rcntm0 time out period max node count 0 0 420 ms up to 255 nodes 0 1 105 ms up to 64 nodes 1 0 52.5 ms up to 32 nodes 1 1 26.25 ms* up to 16 nodes note*: the node id value 255 must exist in the network for 26.25 ms timeout to be valid. address pointer register low 2k x 8 ram 11 data register 8 i/o address 04h i/o address 03h 11-bit counter memory address bus memory data bus d0-d7 high i/o address 02h internal figure 8 C sequential access operation 6.3 internal ram the integration of the 2k x 8 ram in the com20020i 3v represents significant real estate savings. the most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of ra m). in addition, the pc board is now free of the cumbersome external ram, external latch, and multip lexed address/data bus and control functions which were necessary to interface to the ram. the integration of r am represents significant cost savings because it isolates the system designer from the changing costs of external ram and it minimizes reliability problems, assembly time and costs, and layout complexity. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 36 revision 09-11-06 datasheet sequential access memory the internal ram is accessed via a pointer-based scheme. rather than interfering with system memory, the internal ram is indirectly accessed through the address high and low po inter registers. the data is channeled to and from the microcontroller via the 8-bit data register. for example: a packet in the internal ra m buffer is read by the microcontroller by writing the corresponding address into the address pointe r high and low registers (offsets 02h and 03h). note that the high register should be written first, followed by the low register, because writing to the low register loads the address. at this point the device accesses that location and plac es the corresponding data into the data register. the microcontroller then reads the data register (offset 04h) to ob tain the data at the specified location. if the auto increment bit is set to logic "1", the device will automatically increment the address and place the next byte of data i nto the data register, again to be read by the microcontroller. this process is continued until the entire packet is read out of ram. refer to figure 8 for an illustration of the sequential access operat ion. when switching between reads and writes, the pointer must first be written with the starting address. at least one cycle time should sepa rate the pointer being loaded and the first read (see timing parameters). access speed the com20020i 3v is able to accommodate ve ry fast access cycles to its registers and buffers. arbitration to the buffer does not slow down the cycle because the pointer based acce ss method allows data to be prefetched from memory and stored in a temporary register. likewise, data to be written is stored in the temp orary register and then written to memory. for systems which do not require quick access time, the arbi tration clock may be slowed down by setting bit 0 of the setup1 register equal to logic "1". since the slow arbitration feature divides the input clock by two, the d uty cycle of the input clock may be relaxed. software interface the microcontroller interfaces to the com20020i 3v via software by accessing the various registers . these actions are described in the internal registers section. the software flow for accessing the data buffer is based on the sequential access scheme. the basic sequence is as follows: ? disable interrupts ? write to pointer register high (specifying auto-increment mode) ? write to pointer register low (this loads the address) ? enable interrupts ? read or write the data register (repeat as many times as necessary to empty or fill the buffer) ? the pointer may now be read to determine how many transfers were completed. the software flow for controlling the configuration, node id, tentative id, and next id registers is generally limited to the initialization sequence and the maintenance of the network map. additionally, it is necessary to understand the details of how the other internal registers are used in the transmit and receive sequences and to know how the internal ram buffer is properly set up. the sequence of events that tie these actions together is discussed as follows. selecting ram page size during normal operation, the 2k x 8 of ram is divided into four pages of 512 bytes each. the page to be used is specified in the "enable transmit (receive) from (to) page fnn" command, where "nn" specifies page 0, 1, 2, or 3. this allows the user to have constant control over the allocation of ram. when the offset bit "f" (bit 5 of the "enable transmit (recei ve) from (to) page fnn" command word) is set to logic "1", an offset of 256 bytes is added to the page specified. for exampl e: to transmit from the second half of page 0, the command "enable transmit from page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the command register. this allows a finer resolution of the buffer pages without affecting software compatibility. this scheme is useful for applications which frequently use packet sizes of 256 bytes or less, es pecially for microcontroller systems with limited memory capacity. the remaining portions of the buffer pages which are not allocated for curr ent transmit or receive packets may be used as temporary storage for previous network data, packets to be sent later, or as extra memory for the system, which may be indirectly accessed. if the device is configured to handle both long and short packets (see "define configuration" command), then receive pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. in this case, the transmit pages may be made 256 bytes long, leav ing at least 512 bytes free at any given time. even if the command chaining operation is being used, 512 bytes is still guaranteed to be free because command chaining only downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 37 revision 09-11-06 datasheet requires two pages for transmit and two for receive (in this case, two 256 byte pages for transmit and two 512 byte page s for receive, leaving 512 bytes free). please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. the com20020i 3v d oes not check page boundaries during reception. if the device is configured to handle on ly short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1kbyte at any given time. even if the command chaining operation is being used, 1kbyte is still guaranteed to be free because command chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1k free). the general rule which may be applied to determine where in ram a page begins is as follows: address = (nn x 512) + (f x 256). transmit sequence during a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the ram buff er and writes into it. the appropriate buffer size is specified in the "define configuration" comm and. when long packets are enabled, the com20020i 3v interprets the packet as either a long or short packet, depending on whether the buffer add ress 2 contains a zero or non-zero value. the format of the buffer is shown in figu re 9. address 0 contains the source identifier (sid); address 1 contains the destination identifier (did); address 2 (count) contains, for sh ort packets, the value 256-n, where n represents the number of information bytes in the message, or fo r long packets, the value 0, indicating that it is indeed a long packet. in the latter case, address 3 (count) would contain the value 512-n, where n represents the number of information bytes in the message. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 38 revision 09-11-06 datasheet figure 9 C ram buffer packet configuration the sid in address 0 is used by the receiving node to reply to the transmitting node. the com20020i 3v puts the local id in this location, therefore it is not necessary to write into this loca tion. please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes. a minimum value of 257 exists on a long packet so that the count is expressible in eight bits. this leaves three exception packet lengths which do not fit into either a shor t or long packet; packet lengths of 254, 255, or 256 bytes. if packets of these lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit into a long packet. once the packet is written into the buffer, the microcontroller awaits a logic "1 " on the ta bit, indicating that a previous transmit command has concluded and another may be issued. each time the message is loaded and a transmit command issued, it will take a variable amount of time before the message is transmitted, depending on the traffic on the network and the location of the token at the time the tran smit command was issued. the conclusion of the transmit command will generate an interrupt if the interrupt mask allows it. if the device is configured for the command chaining operation, please see the command chaining section for further detail on the transmit sequence. once the ta bit becomes a logic "1", the microcontroller may issue the "enable transmit from page fnn" command, which resets the ta and tma bits to logic "0". if the message is not a broadcast, the com20020i 3v automatically sends a free buffer enquiry to the destination node in order to send the message. at this point, one of four possibilities may sid did count = 256-n not used data byte 1 data byte 2 data byte n-1 data byte n not used sid did 0 count = 512-n not used data byte 1 data byte 2 data byte n-1 data byte n short packet format long packet format a ddress address 01 2 count 255 511 n = data packet length sid = source id did = destination id (did = 0 for broadcasts) 01 2 count 511 3 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 39 revision 09-11-06 datasheet occur. the first possibility is if a free buffer is available at the destination node, in which case i t responds with an acknowledgement. at this point, the com20020i 3v fetches the da ta from the transmit buffer and performs the transmit sequence. if a successful transmit sequence is completed, the tma bit and t he ta bit are set to logic "1". if the packet was not transmitted successfully, tma w ill not be set. a successful transmission occurs when the receiving node responds to the packet with an ack. an unsuccessful transmission occurs when the receiving node does not respond to the packet. the second possibility is if the destination node responds to the free buffer enquiry with a negative acknowledgement. a nak occurs when the ri bit of the destination node is a logic "1". in this case, the token is pass ed on from the transmitting node to the next node. the next time the transmitter receives the token, it will again transmit a free buffer enquiry. if a nak is again received, the token is again passed onto the next node. the excessive nak bit of the diagnostic status register is used to prevent an endless sending of fbe's and nak's. if no limit of fbe-nak sequences existed, the transmitting node would continue issuing a free buffer enquiry, even though it would continuously receive a nak as a response. the excnak bit generates an interrupt (if enabled) in order to tell the microcontroller to disable the transmitter via the "disable transmitter" command. this causes the trans mission to be abandoned and the ta bit to be set to a logic "1" when the node next receives the token, while the tma bit remains at a logic "0". please refer to the improved diagnostics section for further detail on the excnak bit. the third possibility which may occur after a free buffer enquiry is issued is if the destinat ion node does not respond at all. in this case, the ta bit is set to a logic " 1", while the tma bit remains at a logic "0". the user should determine whether the node should try to reissue the transmit command. the fourth possibility is if a non-traditional response is received (some pattern other th an ack or nak, such as noise). in this case, the token is not passed onto the next node, which causes the lost token timer of the next node to time out, thus generating a network reconfiguration. the "disable transmitter" command may be used to cancel any pending transmit command when the com20020i 3v next receives the token. normally, in an active network, this command will set the ta status bit to a logic "1" w hen the token is received. if the "disable transmitter" command does not cause the ta bit to be set in the time it takes the token to make a round trip through the network, one of three si tuations exists. either the node is disconnected from the network, or there are no other nodes on the network, or the external receive circuitry has failed. th ese situations can be determined by either using the improved diagnostic features of the com20020i 3v or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. receive sequence a receive sequence begins with the ri status bit becoming a logic "1", which indicates that a previous recepti on has concluded. the microcontroller will be interrupted if the correspo nding bit in the interrupt mask register is se t to logic "1". otherwise, the microcontroller must periodically check the status register. once the mi crocontroller is alerted to the fact that the previous reception has conc luded, it may issue the "enable receive to page fnn" command, which resets the ri bit to logic "0" and selects a new page in the ram buffer. again, the appropriate buffer s ize is specified in the "define configuration" command. typically, the page which just received the data packet will be read by the microcontroller at this point. once the "enable receive to page fnn" command is issued, the microcontroller attends to other duties . there is no way of knowing how long the new reception will take, since another node may transmit a packe t at any time. when another node does transmit a packet to this node, and if the "define configuration" command has enabled the reception of long packets, the com20020i 3v interprets the packet as either a long or short packe t, depending on whether the content of the buffer location 2 is zero or non-zer o. the format of the buffer is shown in figure 10. address 0 contains the source identifier (sid), address 1 contains the destination identifier (did), and address 2 contai ns, for short packets, the value 256-n, where n represents the message length, or for lo ng packets, the value 0, indicating that it is indeed a long packet. in the latter case, address 3 contains the value 512-n, where n represents the message length. note that on reception, the com20020i 3v deposits packets into the ram buffer in the same format that the transmitting node arranges them, which allows for a message to be received and then retransmitted without rearranging any bytes in the ram buffer other than the sid and did. once the packet is received and stored correctly in the selected buffer, the com20020i 3v sets the ri bit to logic "1" to signal the microcontroller that the reception is complete. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 40 revision 09-11-06 datasheet figure 10 - command chaining status register queue 6.4 command chaining the command chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. through the use of a dual two-level fifo, commands to be tr ansmitted and received, as well as the status bits, are pipelined. in order for the com20020i 3v to be compatible with previous smsc arcnet device drivers, the device defaults to the non-chaining mode. in order to take advantage of the command chaining operation, the command chaining mode must be enabled via a logic "1" on bit 6 of the configuration register. in command chaining, the status register appears as in figure 10. the following is a list of command chaining guidelines for the software progr ammer. further detail can be found in the transmit command chaining and receive command chaining sections. ? the device is designed such that the interrupt service routine latency does not affect performance. ? up to two outstanding transmissions and two outstanding receptions can be pending at any given time. the commands may be given in any order. ? up to two outstanding transmit interrupts and two outstandi ng receive interrupts are stored by the device, along with their respective status bits. ? the interrupt mask bits act on tta (rising transition on transmitter available) for transmit operations and tri (rising transition of receiver inhibited) for receive operations. tta is set upon completion of a packet transmission only. tri is set upon completion of a packet reception only. typically there is no need to mask the tta and tri bits after clearing the interrupt. ? the traditional ta and ri bits are still available to reflect the present status of the devic e. transmit command chaining when the processor issues the first "enable transmit to page fnn" command, the com20020i 3v responds in the usual manner by resetting the ta and tma bits to prepare for the transmission from the specified page. the ta bit can be used to see if there is currently a transmission pending, but the ta bit is really meant to be used in the non-chaining mode only. the tta bits provide the relevant information for the device in the comman d chaining mode. in the command chaining mode, at any time after the first co mmand is issued, the processor can issue a second "enable transmit from page fnn" command. the com20020i 3v stores the fact that the second transmit comman d was issued, along with the page number. after the first transmission is completed, the com20020i 3v updates the status register by setting the tta bit, w hich generates an interrupt. the interrupt service routin e should read the status register. at this point, the tta bit will be found to be a logic "1" and the tma (transmit message acknow ledge) bit will tell the processor whether the transmission was successful. after reading the status register, the "clear transmit interrupt" command is issu ed, thus resetting the tta bit and clearing the interrupt. note that only the "clear transmit interrupt" command will clear the tta bit and the interrupt. it is not necessary, however, to clear the bit or the interrupt right away because the stat us of the transmit tri ri ta por test recon tma tta tma tta tri msb lsb downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 41 revision 09-11-06 datasheet operation is double buffered in order to retain the results of the first transmission for analysis by the pr ocessor. this information will remain in the status register until the "cle ar transmit interrupt" command is issued. note that the interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is acknowledged. the com20020i 3v guarantees a minimum of 2 00ns (at ef=1) interrupt inactive time interval between interrupts. the tma bit is also double buffered to reflect whether the appropriate transmi ssion was a success. the tma bit should only be considered valid after the corresponding tta bit has been set to a logic "1". the tma bit never causes an interrupt. when the token is received again, the second transmission will be automatically initiated after the first is completed by using the stored "enable transmit from page fnn" command. the operation is as if a new "enable transmit from page fnn" command has just been issued. after the first transmit status bits are cleared, the status register will again be updated with the results of the second transmission and a second interrupt resulting from the second transmission will occur. the com20020i 3v guarantees a minimum of 200ns (at ef=1) interrupt inactive time interval before the following edge. the transmitter available (ta) bit of the interrupt mask register now masks only the tta bit of the stat us register, not the ta bit as in the non-chaining mode. since the tta bit is only set upon transmission of a pa cket (not by reset), and since the tta bit may easily be reset by issuing a "clear trans mit interrupt" command, there is no need to use the ta bit of the interrupt mask register to mask interrupts generated by the tta bit of the status register. in command chaining mode, the "disable transmitter" command will cancel the oldest transmission. this permi ts canceling a packet destined for a node not ready to receive. if both packets should be canceled, two "dis able transmitter" commands should be issued. receive command chaining like the transmit command chaining operation, the processor can issue two consecutive "enable receive from page fnn" commands. after the first packet is received into the first specified page, the tri bit of the status register will be set to logic "1", causing an interrupt. again, the interrupt need not be serviced immediately. typically, the interrupt service routine will read the status register. at this point, the ri bit will be f ound to be a logic "1". after reading the status register, the "clear receive interrupt" command should be issued, thus rese tting the tri bit and clearing the interrupt. note that only the "clear receive interrupt" command will clear the tri bit and the interrupt. it is not necessary , however, to clear the bit or the interrupt right away because the status of the receive operation is doub le buffered in order to retain the results o f the first reception for analysis by the processor, therefore the information will rem ain in the status register until the "clea r receive interrupt" command is issued. note that the interrupt will remain acti ve until the "clear receive interrupt" command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. a minimum o f 200ns (at ef=1) interrupt inactive time interval between interrupts is guaranteed. the second reception will occur as soon as a second packet is sent to the node, as long as the second "enable receive to page fnn" command was issued. the operation is as if a new "enable receive to page fnn" command has just been issued. after the first receive status bits are cleared, the status register will again be upd ated with the results of the second reception and a second interrupt resulting from the second reception will occur. in the com20020i 3v, the receive inhibit (ri) bit of the interrupt mask register now masks o nly the tri bit of the status register, not the ri bit as in the non-chaining mode. since the tri bit is only set upon reception of a packet (not by reset), and since the tri bit may easily be reset by issuin g a "clear receive interrupt" command, there is no need to use the ri bit of the interrupt mask register to mask inte rrupts generated by the tri bit of the status register. in command chaining mode, the "disable receiver" command will cancel the oldest reception, unless the reception has already begun. if both receptions should be canceled, two "disable receiver" commands should be issu ed. reset details internal reset logic the com20020i 3v includes special reset circuitry to guarantee smooth operation during reset. sp ecial care is taken to assure proper operation in a variety of systems and modes of operation. the com20020i 3v contains digit al filter circuitry and a schmitt trigger on the nreset signal to re ject glitches in order to ensure fault-free operation. the com20020i 3v supports two reset options; software and hardware reset. a software reset i s generated when a downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 42 revision 09-11-06 datasheet logic "1" is written to bit 7 of the configuration register. the device remains in reset as long as this bit is set. the software reset does not affect the microcontroller interface modes determined after hardware reset, nor does it af fect the contents of the address pointer registers, the configuration register, or the setup1 register. a hardware reset oc curs when a low signal is asserted on the nreset input. the minimum reset pulse width is 5t xtl. this pulse width is used by the internal digital filter, which filters short glitches to allow only valid res ets to occur. upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the internal registers section. after the nreset signal is removed the user may write to the internal registers. since writing a non-zero value to the node id register wakes up the com 20020i 3v core, the setup1 register should be written before the node id register. once the node id register is written to, the com20020i 3v reads the value and executes two write cycles to the ram buffer. address 0 is written with the data d1h and address 1 is w ritten with the node id. the data pattern d1h was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation. 6.5 initialization sequence bus determination writing to and reading from an odd address location from the com20020i 3v's address space causes the com20020i 3v to determine the appropriate bus interface. when the com20020i 3v is powered on the internal regis ters may be written to. since writing a non-zero value to the node id register wakes up the core, the setup1 register shou ld be written to before the node id register. until a non-zero value is placed into th e nid register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are generated by this node. once a non-ze ro value is placed in the register, the core wakes up, but the node will not attempt to join the network until the tx enable bit of the configuration register is set. before setting the tx enable bit, the software may make some determinations. the soft ware may first observe the receive activity and the token seen bits of the diagnostic status register to verify the hea lth of the receiver and the network. next, the uniqueness of the node id value placed in the node id register is determined. the tx enable bit shoul d still be a logic "0" until it is ensured that the node id is unique. if this node id already exists, the dupl icate id bit of the diagnostic status register is set after a maximum of 420ms (or 840ms if the et1 and et2 bits are other than 1,1). to determine if another node on the network already has this id, the com20020i 3v compares the value in the node id register with the did's of the token, and determines whether there is a resp onse to it. once the diagnostic status register is read, the dupid bit is cleared. the user may then attempt a new id value, wait 4 20ms before checking the duplicate id bit, and repeat the process until a unique node id is found. at this point, the tx enable bit may be set to allow the node to join the network. once the node joins the network, a reconfiguration occu rs, as usual, thus setting the myrecon bit of the diagnostic status register. the tentative id register may be used to build a network map of all the nodes on the network, even once the com20020i 3v has joined the network. once a value is plac ed in the tentative id register, the com20020i 3v looks for a response to a token whose did matches the tentative id register. the software can record this information and continue placing tentative id values into the register to continue building the network map. a complete network map is only valid until nodes are added to or deleted from the networ k. note that a node cannot detect the existence of the next logical node on the network when using the tentative id. to determine the next logical node, the software should read the next id register. 6.6 improved diagnostics the com20020i 3v allows the user to better manage the operation of the network through the use of the internal diagnostic status register. a high level on the my reconfiguration (myrecon) bit indicates that the token reception tim er of this node expired, causing a reconfiguration by this node. after the reconfiguration (recon) bit of the s tatus register interrupts the microcontroller, the interrupt service routine will typically read the myrecon bit of the diagnostic status register. reading the diagnostic status register resets the myreco n bit. successive occurrences of a logic "1" on the myrecon bit indicates that a problem exists with this node. at that point, the transmitter should be disabled so that the entire network is not held down while the node is being evaluated. the duplicate id (dupid) bit is used before the node joins the network to ensure that another node with the sa me id does not exist on the network. once it is determined that the id in the node id register is uniq ue, the software should write a logic "1" to bit 5 of the configuration register to enable the basic transmit fu nction. this allows the node to join downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 43 revision 09-11-06 datasheet the network. the receive activity (rcvact) bit of the diagnostic status register will be set to a logic "1" whene ver activity (logic "1") is detected on the rxin pin. the token seen (token) bit is set to a logic "1" whenever any token has been seen on the network (except those tokens transmitted by this node). the rcvact and token bits may help the user to troubleshoot the network or the node. if unusual events are occurring on the network, the user may find it valuable to use the txen bit of the configuration register to qual ify events. different combinations of the rcvact, token, and txen bits, as shown indicate different situation s: normal results: rcvact=1, token=1, txen=0: the node is not part of the network. the network is operating properly without this node. rcvact=1, token=1, txen=1: the node sees receive activity and sees the token. the basic transmit function is enabled. network and node are operating properly. myrecon=0, dupid=0, rcvact=1, txen=0, token=1: single node network. abnormal results: rcvact=1, token=0, txen=x: the node sees receive activity, but does not see the token. either no other nodes exist on the network, some type of data corruption exists, the media driver is malfunctioning, the topology is set up incorrectly, there is noise on the network, or a reconfiguration is occurring. rcvact=0, token=0, txen=1: no receive activity is seen and the basic transmit function is enabled. the transmitter and/or receiver are not functioning properly. rcvact=0, token=0, txen=0: no receive activity and basic transmit function disabled. this node is not connected to the network. the excessive nak (excnak) bit is used to replace a timeout function traditionally implemented in software. this function is necessary to limit the number of times a sender issues a fbe to a node with no available buffer. whe n the destination node replies to 128 fbes with 128 naks or 4 fbes with 4 naks, the excnak bit of the sender is set, generating an interrupt. at this point the software may abandon the transmission via the "disable transmitter" command. this sets the ta bit to logic "1" when the node next receives the token, to allow a diffe rent transmission to occur. the timeout value for the exnack bit (128 or 4) is determined by the four-naks bit on the setup1 register. the user may choose to wait for more nak's before disabling the transmitter by taking advantage of the wraparound counter of the excnak bit. when the excnak bit goes hi gh, indicating 128 or 4 naks, the "por clear flags" command maybe issued to reset the bit so that it will go high again after another count of 128 or 4. the software may count the number of times the excnak bit goes high, and once the final count is reached, the "disable transmitter" command may be issued. the new next id bit permits the software to detect the withdrawal or addition of nodes to the net work. the tentative id bit allows the user to build a network map of those nodes existing on the ne twork. this feature is useful because it minimizes the need for human intervention. when a value placed in the tentative id register matches the node id of another node on the network, the tentid bit is set, telling the software that this node id already exists on the network. the software should periodically place values in the tentative id register and monitor the new next id bit to maintain an updated network map. oscillator the com20020i 3v contains circuitry which, in conjunction with an external parallel resonant crystal or ttl clock, forms an oscillator. if an external crystal is used, two capacitors are needed (one from each leg of the crystal to g round). no external resistor is required, since the com20020i 3v contains an internal resistor. the crystal must have an accuracy of 0.020% downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 44 revision 09-11-06 datasheet or better. the oscillation frequency range is from 10 mhz to 20 mhz. the crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turne d on. the oscillation frequency must be 20mhz when the internal clock multiplier is turned on. the xtal2 side of the crystal may be loaded with a single 74hc-type buffer in order to ge nerate a clock for other devices. the user may attach an external ttl clock, rather than a crystal, to the xtal1 signal. in th is case, a 390 pull-up resistor is required on xtal1, while xtal2 should be left unconnected. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 45 revision 09-11-06 datasheet chapter 7 operational description 7.1 maximum guaranteed ratings* operating temperature range .................................................................................................... .................... -40 o c to +85 o c storage temperature range ...................................................................................................... ...................-55 o c to +150 o c lead temperatur e (soldering, 10 seconds).................................................................................................................+325 o c positive voltage on any pin except xtal 1 and xtal2, with respect to ground .................................................... ......+5.5v positive voltage on xtal1 and xta l2 pin, with respec t to ground ............................................................... .......v dd +0.3v negative voltage on any pin, with respect to ground ............................................................................ ..........................-0.3v maximum v dd .............................................................................................................................. ..................................... +5v *stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition ab ove those indicated in the operational sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maxi mum ratings not be exceeded or device failure can result. some power suppl ies exhibit voltage spikes or "glitches" on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may app ear on the dc output. if this possibility exists it is suggested that a clamp circuit be used. 7.2 dc electrical characteristics v dd =3.3v5% t a =-40 o c to +85 o c parameter symbol min typ max unit comment low input voltage 1 (all inputs except xtal1) high input voltage 1 (all inputs except xtal1) v il1 v ih1 -0.3 2.0 0.8 5.5 v v ttl level low input voltage 2 (xtal1) high input voltage 2 (xtal1) v il2 v ih2 -0.3 0.8xv dd 0.2xv dd v dd +0.3 v v external clock input low output voltage 1 (ntxen) high output voltage 1 (ntxen) v ol1 v oh1 2.4 0.4 v v i sink =4ma i source =-2ma low output voltage 2 (ad0-ad2, d3-d7, nintr, npulse1 in push/pull mode, npulse2) high output voltage 2 (ad0-ad2, d3-d7, nintr, npulse1 in push/pull mode, npulse2) v ol2 v oh2 2.4 0.4 v v i sink =8ma i source =-4ma low output voltage 3 (npulse1 in open-drain mode) v ol3 0.4 v i sink =8ma open drain driver dynamic v dd supply current i dd 40 ma 5 mbps all outputs open downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 46 revision 09-11-06 datasheet parameter symbol min typ max unit comment input pull-up current (npulse1 in open-drain mode, a1, ad0-ad2, d3-d7, bustmg) input leakage current (all inputs except a1, ad0-ad2, d3-d7, xtal1, bustmg) i p i l 80 200 10 a a v in =0.0v v ss < v in < v dd capacitance (t a = 25 c; f c = 1mhz; v dd = 0v) output and i/o pins capacitive load specified as follows: parameter symbol min typ max unit comment input capacitance c in 5.0 pf output capacitance 1 (all outputs except xtal2) c out1 45 pf maximum capacitive load which can be supported by each output. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 47 revision 09-11-06 datasheet 0.4v ac measurements are taken at the following points: inputs: 2.4v1.4v 50% 50% 0.4v 2.4v1.4v 0.8v outputs: 2.0v 0.8v 2.0v inputs are driven at 2.4v for logic "1" and 0.4 v for logic "0" except xtal1 pin. outputs are measured at 2.0v min. for logic "1" and 0.8v max. for logic "0". t t tt downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 48 revision 09-11-06 datasheet chapter 8 timing diagrams figure 11 - multiplexed bus, 68xx-like control signals; read cycle a d0-ad2, valid ncs t1 t3 t8 ale valid data t2, t6 t5 t4 t7 d3-d7 dir t9 t10 nds t11 t12 t13 t14 note 2 parameter min max units t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low nds low to valid data nds high to data high impedance cycle time (nds low to next time low) dir setup to nds active dir hold from nds inactive ale high width ale low width nds low width nds high width 2010 10 10 15 0 4t arb * 10 1020 20 60 20 4020 nsns ns ns ns ns ns ns ns ns ns ns ns ns must be: rbustmg bit = 0 t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. plcc package: must be rbustmg bit = 0, tqfp package: must be bustmg pin = high and rbustmg bit =0 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 49 revision 09-11-06 datasheet figure 12 - multiplexed bus, 80xx-like control signals; read cycle a d0-ad2, valid ncs t1 t3 t8 ale valid data t2, t6 t5 t4 t7 d3-d7 nrd t9 t10 nwr t13 t11 t12 note 3 note 2 ale high width ale low width nrd low width nrd high width nwr to nrd low parameter min max units t1t2 t3 t4 t5 t6 t7 t8t9 t10t11 t12 t13 address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nrd low nrd low to valid data nrd high to data high impedance cycle time (nrd low to next time low) 2010 10 10 15 0 4t arb * 4020 nsns ns ns ns ns ns ns ns ns ns ns ns must be: rbustmg bit = 0 2020 60 20 20 the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. note 3: read cycle for address pointer low/high registers occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd. plcc package: must be rbustmg bit = 0, tqfp package: must be bustmg pin = high and rbustmg bit =0 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 50 revision 09-11-06 datasheet figure 13 - multiplexed bus, 68xx-li ke control signals; write cycle a d0-ad2, valid ncs t1 t3 t8 ale val id data t2, t6 t5 t4 t7 d3-d7 dir t9 t10 note 2 t8** nds t11 t12 t13 t14 parameter min max units t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 2010 10 10 15 10 4t arb * 10 1020 20 20 20 nsns ns ns ns ns ns ns ns ns ns ns ns ns address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low valid data setup to nds high data hold from nds high dir setup to nds active dir hold from nds inactive 30 ale high width ale low width nds low width nds high width cycle time (nds to next )** the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: any cycle occurring after a write to address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. note 2: ** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits write cycle for address pointer low register occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. plcc packa g e: dont care rbustmg bit, tqfp packa g e: must be bustmg p in = high downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 51 revision 09-11-06 datasheet figure 14 - multiplexed bus, 80xx-li ke control signals; write cycle a d0-ad2, valid ncs t1 t3 ale valid data t2, t6 t5 t4 t7 d3-d7 note 2 t8** nwr t9 t10 nrd t13 t11 t12 t8 note 3 parameter min max units t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 2010 10 10 15 10 4t arb * 2020 20 20 20 nsns ns ns ns ns ns ns ns ns ns ns ns address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low valid data setup to nds high data hold from nds high 30 ale high width ale low width nwr low width nwr high width nrd to nwr low cycle time (nwr to next )** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: any cycle occurring after a write to address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. note 2: ** write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. note 3: write cycle for address pointer low register occurring after a read from da ta register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr. plcc packa g e: dont care rbustmg bit, tqfp packa g e: must be bustmg p in = high downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 52 revision 09-11-06 datasheet figure 15 - non-multiplexed bus, 80xx-like control signals; read cycle a 0-a2 valid data valid d0-d7 ncs t6 t1 t7 t3 t5 t4 t2 nrd nwr t10 t8 t9 note 3 note 2 parameter min max units t1t2 t3 t4 t5t6 t7t8 t9 t10 1510 5**0 nsns ns ns address setup to nrd active address hold from nrd inactive ncs setup to nrd active ncs hold from nrd inactive cycle time (nrd low to next time low) nrd low to valid data nrd high to data high impedance 4t arb * 0 6020 20 40** 20 nsns ns ns nsns case 1: rbustmg bit = 0 nrd low width nrd high width nwr to nrd low t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits ncs may become active after control becomes active, but the access time (t6) will now be 45ns measured from the leading edge of ncs. ** the microcontroller typically accesses the com20020 on every other cy cle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: note 2: read cycle for address pointer low/high registers occurring after a rea d from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. note 3: read cycle for address pointer low/high registers occurring after a wri te to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd. ** case 1 plcc package: must be rbustmg bit = 0, tqfp package: must be bustmg pin = high and rbustmg bit =0 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 53 revision 09-11-06 datasheet figure 16 - non-multiplexed bus, 80xx-like control signals; read cycle a 0-a2 valid data valid d0-d7 ncs t6 t1 t7 t3 t5 t4 t2 nrd nwr t10 t8 t9 note 3 note 2 parameter min max units t1t2 t3 t4 t5t6 t7t8 t9 t10 -5 0 -5 0 nsns ns ns address setup to nrd active address hold from nrd inactive ncs setup to nrd active ncs hold from nrd inactive cycle time (nrd low to next time low) nrd low to valid data nrd high to data high impedance 4t arb *+30 0 100 3020 60** 20 nsns ns ns nsns nrd low width nrd high width nwr to nrd low case 2: rbustmg bit = 1 the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: t6 is measured from the latest active (valid) timing among ncs, nrd, a0-a2. ** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after a read fr om data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. note 3: read cycle for address pointer low/high registers occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd. c a se 2 plcc package: must be rbustmg bit = 1, tqfp package: must be bustmg pin = low or rbustmg bit =1 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 54 revision 09-11-06 datasheet figure 17 - non-multiplexed bus, 68xx-like control signals; read cycle a0-a2 valid data valid d0-d7 ncs t8 t1 t9 t3 t6 t4 t2 nds dir t5 t7 t10 t11 note 2 parameter min max units t1 t2 t3t4 t5 t6 t7 15 10 5** 0 ns address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds low to next time low) dir hold from nds inactive 4t arb * ns ns nsns nsns t8 ns nds low to valid data 40** t9 t10 t11 nsns ns nds high to data high impedence nds low width nds high width 20 10 10 0 6020 case 1: rbustmg bit = 0 the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: ncs may become active after control becomes active, but the access time (t8) will now be 45ns measured from the leading edge of ncs. ** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. case 1 plcc package: must be rbustmg bit = 0, tqfp package: must be bustmg pin = high and rbustmg bit =0 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 55 revision 09-11-06 datasheet figure 18 - non-multiplexed bus, 68xx-like control signals; read cycle a0-a2 valid data valid d0-d7 ncs t8 t1 t9 t3 t6 t4 t2 nds dir t5 t7 t10 t11 note 2 parameter min max units t1 t2 t3t4 t5 t6 t7 -5 0 -5 0 ns address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds low to next time low) dir hold from nds inactive 4t arb *+30 ns ns nsns ns ns t8 ns nds low to valid data 60** t9 t10t11 nsns ns nds high to data high impedence nds low width nds high width 20 1010 0 100 30 case 2: rbustmg bit = 1 the microcontroller typically accesses the com20020 on every other cycle . therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: ** t8 is measured from the latest active (valid) timing among ncs, nds, a0-a2. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. case 2 plcc package: must be rbustmg bit = 1, tqfp package: must be bustmg pin = low or rbustmg bit =1 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 56 revision 09-11-06 datasheet figure 19 - non-multiplexed bus, 80xx-like control signals; write cycle data hold from nwr high nwr low width nwr high width nrd to nwr low a0-a2 valid data valid d0-d7 ncs t6 t1 t7 t3 t4 t2 note 2 nwr nrd t10 t8 t9 t5 note 3 t5** t1 t3 t5 t6 t7t8 t9 t10 parameter address setup to nwr active ncs setup to wr active valid data setup to nwr high min 15 5 1020 20 20 max 4t arb * 30*** units ns ns ns nsns ns ns ns t4 ncs hold from nwr inactive 0 ns t2 address hold from nwr inactive 10 ns cycle time (nwr to next )** ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datashe et should be doubled when considering back-to-back com20020 cycles. note 1: note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. note 3: write cycle for address pointer low register occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr. ** case 1 plcc package: dont care rbustmg bit, tqfp package: must be bustmg pin = high downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 57 revision 09-11-06 datasheet figure 20 - non-multiplexed bus, 80xx-like control signals; write cycle data hold from nwr high nwr low width nwr high width nrd to nwr low a0-a2 valid data valid d0-d7 ncs t6 t1 t7 t3 t4 t2 note 2 nwr nrd t10 t8 t9 t5 note 3 t5** t1 t3 t5 t6 t7t8 t9 t10 parameter address setup to nwr active ncs setup to wr active valid data setup to nwr high min 15 5 1020 20 20 max 4t arb * 30*** units ns ns ns nsns ns ns ns t4 ncs hold from nwr inactive 0 ns t2 address hold from nwr inactive 10 ns cycle time (nwr to next )** ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datashe et should be doubled when considering back-to-back com20020 cycles. note 1: note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. note 3: write cycle for address pointer low register occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr. ** 0 0 0 0 4t arb * 30 10 65 30 20 case 2 plcc packa g e: not su pp orted , tqfp packa g e: must be bustmg p in = low c a s e 2 is su pp orted f or t q fp packa g e o nly downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 58 revision 09-11-06 datasheet figure 21 - non-multiplexed bus, 68xx-like control signals; write cycle a0-a2 vali d data valid d0-d7 ncs t8 t1 t9 t3 t10 t4 t2 note 2 t5 dir t7 nds t11 t6 t6** parameter min max units address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds to next time )** dir hold from nds inactive valid data setup to nds high data hold from nds high nds low width nds high width t1t2 t3 t4 t5 t6 t7 t8 t9 t10t11 1510 50 10 4t arb * 10 30*** 1020 20 nsns ns ns ns ns ns ns ns ns ns ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: **note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. write cycle for address pointer low registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. case 1 plcc package: dont care rbustmg bit, tqfp package: must be bustmg pin = high downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 59 revision 09-11-06 datasheet figure 22 - non-multiplexed bus, 68xx-like control signals; write cycle a0-a2 vali d data valid d0-d7 ncs t8 t1 t9 t3 t10 t4 t2 note 2 t5 dir t7 nds t11 t6 t6** parameter min max units address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds to next time )** dir hold from nds inactive valid data setup to nds high data hold from nds high nds low width nds high width t1t2 t3 t4 t5 t6 t7 t8 t9 t10t11 1510 50 10 4t arb * 10 30*** 1020 20 nsns ns ns ns ns ns ns ns ns ns ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits the microcontroller typically accesses the com20020 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20020 cycles. note 1: **note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. write cycle for address pointer low registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. 0 0 0 0 10 4t arb * 10 30 10 65 30 case 2 plcc packa g e: not su pp orted , tqfp packa g e: must be bustmg p in = low c a s e 2 is su pp orted f or t q fp packa g e o nly downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 60 revision 09-11-06 datasheet figure 23 C normal mode transmit or receive timing (these signals are to and from the hybrid) npulse2 t1t3 t7 t8 parameter npulse1, npulse2 pulse width npulse1, npulse2 overlap rxin period rxin inactive pulse width min 100 -10 max units nsns npulse1 t1 t6 rxin active pulse width t2 t2 npulse1, npulse2 period ns t1 t3 400 0 +10 typ rxin t6 t7 10 400 ntxen nsns t2 t4 t5 last bit (400 ns bit time) t4 ntxen low to npulse1 low 850 950 ns t5 beginning of last bit time to ntxen high 250 350 ns 100 t8 20 ns note: use only 2.5 mbps downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 61 revision 09-11-06 datasheet figure 24 C backplane mode transmit or receive timing (these signals are to and from the differential driver or the cable) npulse1 t2 t3 rxin t10 t11 npulse2 t5 t6 (internal clk) t4 parameter min typ max units t2t3 t4 t5 t6 t7 t8 t10t11 t12 npulse1 pulse width npulse1 period npulse2 low to npulse1 low npulse2 high time npulse2 low time npulse2 period npulse2 high to ntxen high rxin active pulse width rxin period nsns ns ns ns ns ns nsns 200*400* 100* 100* 200* 200* 400* 5050 -25 10 t1 t7 ntxen t9 t8 last bit (400 ns bit time) t1 npulse2 high to ntxen low -25 50 ns (first rising edge on npulse2 after last bit time) t9 ntxen low to first npulse1 low** 650 750 ns t13 t12 -25 rxin inactive pulse width 20 ns t13 beginning last bit time to ntxen high** 450 ns above values are for 2.5 mbps. other data rates are shown below. 550 t dr is the data rate period *t5, t6 = t dr /4 *t2, t7, t10 = t dr /2 *t3, t11 = t dr **t9 = x t dr +/- 50 ns 7 4 **t13 = x t dr +/- 50 ns 5 4 downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 62 revision 09-11-06 datasheet figure 25 C ttl input timing on xtal1 pin figure 26 C reset and interrupt timing t1 parameter nreset pulse width*** min max units nreset t1 t2 nintr high to next nintr low typ t2 nintr 5t xtl * ef = 0ef = 1 t dr **/2 4t xtl * note*: t xtl is period of external xtal oscillation frequency. note**: t dr is period of data rate (i.e. at 2.5 mbps, t dr = 400 ns) note***: when the power is turned on, t1 is measured from stable xtal oscillation after v dd was over 3v. t1t3 parameter input clock high time input clock period* min 2050 max units nsns xtal1 t1 t4 input clock frequency* 100 t2 input clock low time ns t3 20 typ 10 t2 20 mhz t5 frequency accuracy* -200 200 ppm note*: input clock frequency must be 20 mhz ( 100ppm or better) to use the internal clock multip lier. + - t 4 and t 5 are applied to crystal oscillaton. 4.0v 1.0v 50% of v dd downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 63 revision 09-11-06 datasheet chapter 9 package outlines figure 27 - 28 pin plcc package dimensions aa1 b b1 c d d1 d2 d3 e f g r .160-.180 .090-.120 .013-.021 .026-.032 .020-.045 .485-.495 .450-.456 .390-.430 .300 ref .050 bsc .042-.056 .042-.048 .025-.045 dim 28l j .000-.020 notes: all dimensions are in inches. circle indicating pin 1 can appear on a top surface as shown on the drawing or right above it on a beveled edge. 1. 2. pin no. 1 g e j d3 j d1 d j b1 b a a1 c d2 f r b a s e p l a n e s e a t i n g p l a n e downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 64 revision 09-11-06 datasheet figure 28 - 48 pin tqfp package outline min nominal max remark a ~ ~ 1.6 overall package height a1 0.05 0.10 0.15 standoff a2 1.35 1.40 1.45 body thickness d 8.80 9.00 9.20 x span d/2 4.40 4.50 4.60 1 / 2 x span measure from centerline d1 6.90 7.00 7.10 x body size e 8.80 9.00 9.10 y span e/2 4.40 4.50 4.60 1 / 2 y span measure from centerline e1 6.90 7.00 7.10 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length from centerline l1 ~ 1.00 ~ lead length e 0.50 basic lead pitch 0 o ~ 7 o lead foot angle w 0.17 ~ 0.27 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.0762 coplanarity (assemblers) ccc ~ ~ 0.08 coplanarity (test house) note 1: controlling unit: millimeter downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 65 revision 09-11-06 datasheet chapter 10 appendix a this appendix describes the function of the nosync and ef bits. nosync bit the nosync bit controls whether or not the ram initialization sequence requires the line to be idle by enabling or disabling the sync command during initia lization. it is defined as follows: nosync: enable/disable sync command during initialization. nosync=0, enable (default): the line has to be idle for the ram initialization sequence to be written, nosync=1, disable: the line does not have to be idle for the ram initialization sequence to be written. the following discussion describes the function of this bit: during initialization, after the cpu writes the node id, the com20020i 3v will write "d1"h data to address 000h and node-id to address 001h of its internal ram within 6us. thes e values are read as part of the diagnostic test. if the d1 and node-id initialization sequence cannot be read, the initialization routine will report it as a device diagnostic failure. these writes are controlled by a micro-program which someti mes waits if the line is active; sync is the micro-program command that causes the wait. when the micro-program waits, the initial ram write does not occur, which causes the diagnostic error. thus in this case, if the line is not id le, the initialization sequence may not be written, which will be reported as a device diagnostic failure. however, the initialization sequence and diagnostics of the com20020i 3v should be independent of the network status. this is accomplished through some additional logic to decode the program counter, enabled by the nosync bit. when it finds that the micro-program is in the initialization r outine, it disables the sync command. in this case, the initialization will not be held up by the line status. thus, by setting the nosync bit, the line does not have to be idle for the ram initialization sequence to be written. ef bit the ef bit controls several modifications to internal operation timing and logic. it is defined as follows: ef: enable/disable the new internal operation timing and logic refinements. ef=0: (default) disable the new internal operation timing (the timing is the same as in the com20020i rev. b); ef=1: enable the new internal operation timing. the ef bit controls the following timing/logic refinements in the com20020i 3v: a) extend interrupt disable time while the interrupt is active (nintr pin=0), the interrupt is disabled by writing the clear tx/rx interrupt and clear flag command and by reading the next-id register. this minimum disable time is changed by the data rate. for example, it is 200 ns at 2.5 mbps and 100 ns at 5 mbps. the 100 ns width will be too short to for the interrupt to be seen. setting the ef bit will change the minimum disable time to always be more than 200 ns even if the data rate is 5 mbps . this is done by changing the clock which is supplied to the interrupt disable logic. the frequency of this clock is always less than 20mhz even if the data rate is 5 mbps. b) synchronize the pre-scalar output the pre-scalar is used to change the data rate. the output clo ck is selected by ckp3-1 bits in the set-up register. the ckp3-1 bits are changed by writing the set-up register from outside the cpu. it's not synchronized between the cpu and com20020i 3v. thus, changing the ckp3-1 timing does not synchronize with the internal clocks of pre-scalar, and changing ckp3-1 may cause spike noise to appear on the output clock line. setting the ef bit will include flip-flops inserted between th e configuration register and pre-scalar for synchronizing the ckp3-1 with pre-scalars internal clocks. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 66 revision 09-11-06 datasheet never change the ckp3-1 when the data rate is over 5 mbps. they must all be zero. c) shorten the write interval time to the command register the com20020i 3v limits the write interval time for continuous writing to the command register. the minimum interval time is changed by the data rate. it's 100 ns at the 2.5 mbps and 1.6 s at the 156.25 kbps. this 1.6 s is very long for cpu. setting the ef bit will change the clock source from osck cl ock (8 times frequency of data rate) to xtal clock which is not changed by the data rate, such that the minimum interval time becomes 100 ns. d) eliminate the write prohibition period for the enable tx/rx commands the com20020i 3v has a write prohibition period for wr iting the enable transmit/receive commands. this period is started by the ta or ri bit (status reg.) returning to high. this prohibition period is caused by setting the ta/ri bit with a pulse signal. it is 3.2 s at 156.25 kbps. this period may be a problem when using interrupt processing. the interrupt occurrs when the ri bit returns to high. the cpu writes the next enable rece ive command to the other page immediately. in this case, the interval time betwe en the interrupt and writing command is shorter than 3.2 s. setting the ef bit will cause the ta/ri bit to return to hi gh upon release of the pulse signal for setting the ta/ri bit, instead of at the start of the pulse. this is illustrated in figure 29. tx/rx completed ta/ri bit setting pulse nintr pin prohibition period ef=1 tx/rx completed ta/ri bit setting pulse nintr pin ef=0 figure 29 - effect of the ef bit on the ta/ri bit downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 67 revision 09-11-06 datasheet the ef bit also controls the resolution of the following issues from the com20020i rev. b: a) network map generation tentative id is used for generating the network map, but it sometimes detects a non-existent node. every time the tentative-id register is written, the effe ct of the old tentative-id remains active for a while, which results in an incorrect network map. it can be avoided by a carefully coded softwa re routine, but this requires the programmer to have deep knowledge of how the com20020i 3v wor ks. duplicate-id is mainly used fo r generating the network map. this has the same issue as tentative-id. a minor logic change clears all the remaining effects of the old tentative-id and the old duplicate-id, when the com20020i 3v detects a write operation to tentative-id or node-id regist er. with this change, programmers can use the tentative-id or duplicate-id for generating the network map without any issues. this change is enabled/disabled by the ef bit. b) mask register reset the mask register is reset by a soft reset in the com20020i 3v rev. a, but is not reset in rev. b. the mask register is related to the status and diagnostic register, so it should be reset by a soft reset. otherwise, every time the soft reset happens, the com20020i 3v rev. b generates an unnecessary interrupt since the status bits ri and ta are back to one by the soft reset. this is resolved by changing the logic to reset the mask register both by the hard reset and by the soft reset. the soft reset is activated by the node-id regist er going to 00h or by the reset bit going to high in the configurat ion register. this solution is enabled/disabled by the ef bit. downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 68 revision 09-11-06 datasheet chapter 11 appendix b figure 30 - example of interface circuit diagram to isa bus isa bus a en sa15-sa4 sd7-sd0 nior niow sa2-sa0 irqm niocs16 drqn ndack tc nrefresh resetdrv 12 12 bit comparators ls688x2 ng p p=q q i/o address seeting (dip switches) 16 bit bus transceivers ls245 a b dir ng 3 d7-d0 nrd nwr a 2-a0 nintr nreset ncs 8 3 schmitt-trigger buffe r 12 com20020i 8 a downloaded from: http:///
5mbps arcnet (ansi 878.1) contro ller with 2k x 8 on-chip ram smsc com20020i 3.3v rev.e page 69 revision 09-11-06 datasheet chapter 12 appendix c 12.1 software identification of the com20020i 3v rev d and rev e in order to properly write software to work with the com2 0020i 3v rev d and e it is necessary to be able to identify the different revisions of the part. to identify the com20020i 3v revision follow the following procedure: 1. write 0x00 to register-5 2. read register-5 ? the value read from register-5 must be 0x00. 3. write 0xc0 to register-5 4. read register-5* * if the value read from register-5 is 0x80 then the part is a com20020i 3v rev d * if the value read from register-5 is 0xc0 then the part is a com20020i 3v rev e downloaded from: http:///

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